參數(shù)資料
型號(hào): MC68HC05L1FU
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 34/102頁
文件大?。?/td> 632K
代理商: MC68HC05L1FU
MC68HC05L1
MOTOROLA
5-1
PROGRAMMABLE TIMER
5
PROGRAMMABLE TIMER
The programmable timer on the MC68HC05L1 consists of a 16-bit read-only free-running counter,
with a xed divide-by-four prescaler, plus input capture/output compare circuitry. This timer can be
used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from several microseconds to many
seconds. Figure 5-1 shows a block diagram for the Programmable Timer.
The timer has a 16-bit architecture, hence each specic functional segment is represented by two
8-bit registers (high byte and low byte). Generally, assessing the low byte of a specic timer
function allows full control of that function; however, an access of the high byte inhibits that specic
timer function until the low byte is also accessed.
Note:
The I bit in the condition code register should be set while manipulating both the high
and low byte register of a specic timer function to ensure that an interrupt does not
occur.
Fourteen 8-bit registers are associated with the programmable timer.
Timer Control Register (TCR)
$12
Timer Status Register (TSR)
$13
Input Capture Register 1
High byte - $14, Low byte - $15
Output Compare Register 1
High byte - $16, Low byte - $17
Counter Register
High byte - $18, Low byte - $19
Alternate Counter Register
High byte - $1A, Low byte - $1B
Input Capture Register 2
High byte - $1C, Low byte - $1D
Output Compare Register 2
High byte - $1E, Low byte - $1F
A description of each register is provided in the following paragraphs.
TPG
35
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