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參數(shù)資料
| 型號： | MC68HC05L1FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 39/102頁 |
| 文件大小： | 632K |
| 代理商： | MC68HC05L1FU |
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MC68HC05L1
MOTOROLA
5-5
PROGRAMMABLE TIMER
5
5.2.2
Input Capture Register 2 (ICR2)
The two 8-bit registers that make up the 16-bit Input Capture register 2 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit senses
a negative transition at pin TCAP2. When an input capture 2 occurs, the corresponding ag ICF2
in TSR is set. An interrupt can also accompany an input capture 2 provided the ICIE bit in the TCR
is set. The 8 most signicant bits are stored in the Input Capture High 2 register at $1C, the 8 least
signicant bits in the Input Capture Low 2 register at $1D.
The results obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. The delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the Input
Capture register 2 on each negative signal transition whether the input capture 2 ag (ICF2) is set
or clear. The Input Capture register 2 always contains the free-running counter value that
corresponds to the most recent input capture 2. After a read of the Input Capture 2 register MSB
($1C), the counter transfer is inhibited until the LSB ($1D) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the Input Capture 2 register LSB ($1D) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the Input Capture 2 register, except when exiting Stop mode.
5.3
Output Compare
‘Output Compare’ is a technique which may be used, for example, to generate an output
waveform, or to signal when a specic time period has elapsed, by presetting the output compare
register to the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2).
The same output compare interrupt enable bit (OCIE) is used for the two output compares.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Input capture high 2
$001C
unaffected
Input capture low 2
$001D
unaffected
TPG
39
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