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參數(shù)資料
| 型號(hào)： | MC68HC05JB4DWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 85/134頁(yè) |
| 文件大?。?/td> | 1305K |
| 代理商： | MC68HC05JB4DWR2 |
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GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
MULTI-FUNCTION TIMER
MC68HC05JB4
8-2
REV 2
8.1
OVERVIEW
As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by
four. NTF1 has the same phase and frequency as the processor bus clock, PH2,
but continues to run in WAIT mode. The NTF1 drives an 8-bit ripple counter. The
value of this 8-bit ripple counter can be read by the CPU at any time by accessing
the Timer Counter Register (TCNT) at address $09. A timer overow function is
implemented on the last stage of this 8-bit counter, giving a possible interrupt rate
of fOP÷1024.
The last stage of the 8-bit counter also drives a further 7-bit counter. The nal four
stages is used by the RTI circuit, giving possible RTI rates of fOP÷2
14, 215, 216 or
RTI and TOF enable bits and ags are located in the Timer Control and Status
Register at location $08.
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 128 or 4064 cycles, the power-on reset circuit is released which
again clears the counter chain and allows the device to come out of reset. At this
point, if RESET is not asserted, the timer will start counting up from zero and nor-
mal device operation will begin. If RESET is asserted at any time during operation
the counter chain will be cleared.
8.2
COMPUTER OPERATING PROPERLY (COP) WATCHDOG
The COP Watchdog is enabled by a mask option.
The COP Watchdog Timer function is implemented by using the output of the RTI
circuit and further dividing it by eight. The minimum COP reset rates are listed in
Table 8-1. If the COP circuit times out, an internal reset is generated and the nor-
mal reset vector is fetched.
Preventing a COP time-out is done by writing a “0” to bit-0 of address $1FF0.
When the COP is cleared, only the nal divide by eight stage (output of the RTI) is
cleared.
Table 8-1. RTI and COP Rates at fOP=3.0MHz
Bus Frequency, fBUS=fOP=3.0 MHz
RT1
RT0
Divide Ratio
RTI Rate
COP Reset Period
(RTI x 8)
00
214
5.46ms
43.68ms
01
215
10.92ms
87.36ms
10
216
21.85ms
174.8ms
11
217
43.69ms
349.52ms
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