參數(shù)資料
型號： MC68HC05JB4DWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 121/134頁
文件大?。?/td> 1305K
代理商： MC68HC05JB4DWR2
February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
UNIVERSAL SERIAL BUS MODULE
MOTOROLA
REV 2
10-21
EOPF — End of Packet Detect Flag
This read only bit is set when a valid End-of-Packet sequence is detected on
the D+ and D– lines. Software must clear this ag by writing a logic 1 to the
EOPFR bit.
Reset clears this bit. Writing a logic 0 to EOPF has no effect.
1 =
End-of-Packet sequence has been detected
0 =
End-of-Packet sequence has not been detected
RESUMF — Resume Flag
This read only bit is set when USB bus activity is detected while the SUSPND
bit is set. Software must clear this ag by writing a logic 1 to the RESUMFR bit.
Reset clears this bit. Writing a logic 0 to RESUMF has no effect.
1 =
USB bus activity has been detected
0 =
No USB bus activity has been detected
RESUMFR — Resume Flag Reset
Writing a logic 1 to this write only bit will clear the RESUMF bit if it is set. Writ-
ing a logic 0 to RESUMFR has no effect. Reset clears this bit.
TXD1IE — Endpoint 1/Endpoint 2 Transmit Interrupt Enable
This read/write bit enables the USB to generate an interrupt when the shared
Transmit Endpoint 1/Endpoint 2 interrupt ag (TXD1F) bit becomes set. Reset
clears this bit.
1 =
USB interrupts enabled for Transmit Endpoints 1 and 2
0 =
USB interrupts disabled for Transmit Endpoints 1 and 2
EOPIE — End of Packet Detect Interrupt Enable
This read/write bit enables the USB to generate an interrupt when the EOPF bit
becomes set. Reset clears this bit.
1 =
USB interrupts enabled for Transmit Endpoints 1 and 2
0 =
USB interrupts disabled for Transmit Endpoint 1 and 2
TXD1FR — Endpoint 1/Endpoint 2 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD1F bit if it is set. Writing a
logic 0 to TXD1FR has no effect. Reset clears this bit.
EOPFR — End of Packet Flag Reset
Writing a logic 1 to this write only bit will clear the EOPF bit if it is set. Writing a
logic 0 to the EOPFR has no effect. Reset clears this bit.
10.5.4 USB Control Register 0 (UCR0)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UCR0
R
T0SEQ
STALL0
TX0E
RX0E
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
$003B
W
reset:
00000000
Figure 10-23. USB Control Register 0 (UCR0)
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