參數(shù)資料
型號： MC68HC05JB4DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 32/134頁
文件大?。?/td> 2440K
代理商： MC68HC05JB4DW
February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
REV 2
APPENDIX A
MC68HC705JB4
This
appendix
describes
the
MC68HC705JB4,
the
emulation
part
for
MC68HC05JB4. The
entire
MC68HC05JB4
data
sheet
applies
to
the
MC68HC705JB4, with exceptions outlined in this appendix.
A.1
INTRODUCTION
The MC68HC705JB4 is an EPROM version of the MC68HC05JB4, and is avail-
able for user system evaluation and debugging. The MC68HC705JB4 is function-
ally identical to the MC68HC05JB4 with the exception of the 3584 bytes user
ROM is replaced by 3584 bytes user EPROM. Also, the mask options available on
the MC68HC05JB4 are implemented using the Mask Option Register (MOR) in
the MC68HC705JB4.
A.2
MEMORY
The MC68HC705JB4 memory map is shown in Figure A-1.
A.3
MASK OPTION REGISTER (MOR)
The Mask Option Register (MOR) is a byte of EPROM used to select the features
controlled by mask options on the MC68HC05JB4. In order to program this regis-
ter the MORON bit in PCR need to be set to “1” before doing the EPROM pro-
gramming process.
COPEN – COP Enable
1 =
COP watchdog function disabled.
0 =
COP watchdog function enabled.
IRQTRIG – IRQ, PA0-PA3 Interrupt Options
1 =
Edge-trigger only.
0 =
Edge-and-level-triggered.
HIGHCURRA – PA6 and PA7 High Current Enable
1 =
High current capability disabled on PA6 and PA7.
0 =
High current capability enabled on PA6 and PA7.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MOR
R
COPEN
IRQTRIG HIGHCURRA PAINTEN
OSCDLY
LVREN
$007F
W
reset:
00111111
F
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sc
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le
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ic
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to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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.
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