參數(shù)資料
型號： MC68HC05JB4DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 119/134頁
文件大?。?/td> 2440K
代理商： MC68HC05JB4DW
February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
UNIVERSAL SERIAL BUS MODULE
REV 2
USBEN — USB Module Enable
This read/write bit enables and disables the USB module and the USB pins.
When USBEN is clear, the USB module will not respond to any tokens. Reset
clears this bit.
1 =
USB function enabled
0 =
USB function disabled
UADD6-UADD0 — USB Function Address
These bits specify the USB address of the device. Reset clears these bits.
10.5.2 USB Interrupt Register 0 (UIR0)
TXD0F — Endpoint 0 Data Transmit Flag
This read only bit is set after the data stored in Endpoint 0 transmit buffers has
been sent and an ACK handshake packet from the host is received. Once the
next set of data is ready in the transmit buffers, software must clear this ag by
writing a logic 1 to the TXD0FR bit. To enable the next data packet transmis-
sion, TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake will
be returned in the next IN transaction.
Reset clears this bit. Writing a logic 0 to TXD0F has no effect.
1 =
Transmit on Endpoint 0 has occurred
0 =
Transmit on Endpoint 0 has not occurred
RXD0F — Endpoint 0 Data Receive Flag
This read only bit is set after the USB module has received a data packet and
responded with an ACK handshake packet. Software must clear this ag by
writing a logic 1 to the RXD0FR bit after all of the received data has been read.
Software must also set RX0E bit to one to enable the next data packet recep-
tion. If RXD0F bit is not cleared, a NAK handshake will be returned in the next
OUT transaction.
Reset clears this bit. Writing a logic 0 to RXD0F has no effect.
1 =
Receive on Endpoint 0 has occurred
0 =
Receive on Endpoint 0 has not occurred
RSTF — USB Reset Flag
This read only bit is set when a valid reset signal state is detected on the D+
and D– lines. This reset detection will also generate an internal reset signal to
reset the CPU and other peripherals including the USB module. This bit is
cleared by a POR reset.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UIR0
R
TXD0F
RXD0F
RSTF
SUSPND
TXD0IE
RXD0IE
00
$0039
W
TXD0FR
RXD0FR
reset:
00000000
= Unimplemented
Figure 10-21. USB Interrupt Register 0 (UIR0)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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