參數(shù)資料
型號： MC68HC05JB4DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 3/134頁
文件大小： 2440K
代理商： MC68HC05JB4DW
GENERAL RELEASE SPECIFICATION
February 24, 1999
ANALOG TO DIGITAL CONVERTER
REV
11.1
ADC OPERATION
As shown in Figure 11-1, the ADC consists of an analog multiplexer, an 8-bit digi-
tal to analog capacitor array, a comparator and a successive approximation regis-
ter (SAR).
There are ten options that can be selected by the multiplexer; the AD0 to AD5
input pins, VRH, VRL, (VRH+VRL)/4, or (VRH+VRL)/2. Selection is done via the CHx
bits in the ADC Status and Control Register. AD0 to AD5 are input points for ADC
conversion operations; the others are reference points which can be used for test
purposes. The converter uses VRH and VRL as reference voltages. An input volt-
age equal to or greater than VRH converts to $FF. An input voltage equal to or less
than VRL, but greater than VSS, converts to $00. Maximum and minimum ratings
must not be exceeded. Each analog input source should use VRH as the supply
voltage and should be referenced to VRL for the ratiometric conversions. To main-
tain full accuracy of the ADC, the following should be noted:
1.
VRH should be equal to or less than VCC;
2.
VRL should be equal to or greater than VSS but less than maximum
specications; and
3.
VRH–VRL should be equal to or greater than 4 Volts.
The ADC reference inputs (VRH and VRL) are applied to a precision internal digital
to analog converter. Control logic drives this D/A converter and the analog output
is successively compared with the selected analog input sampled at the beginning
of the conversion. The conversion is monotonic with no missing codes.
The result of each successive comparison is stored in the successive approxima-
tion register (SAR) and, when the conversion is complete, the contents of the SAR
are transferred to the read-only ADC Data Register ($0F), and the conversion
complete ag, COCO, is set in the ADC Status and Control Register ($0E).
NOTE
Any write to the ADC Status and Control Register will abort the current
conversion, reset the conversion complete ag (COCO) and a new conversion
starts on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared, thus
the ADC is disabled.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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