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| 型號(hào)： | MC68HC05JB3JP |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 79/148頁(yè) |
| 文件大?。?/td> | 1600K |
| 代理商： | MC68HC05JB3JP |
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GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
INTERRUPTS
MC68HC05JB3
4-6
REV 1
IRQPU — IRQ pin PUll-up resistor enable
This bit enables/disables the internal pull-up resistor on the IRQ pin.
1 =
Internal pull-up resistor in IRQ pin enabled.
0 =
Internal pull-up resistor in IRQ pin disabled.
IRQR — IRQ Interrupt Acknowledge
This write-only bit clears an IRQ interrupt by clearing the IRQ latch, and hence
the IRQF bit. The IRQR bit will always read as a logic zero.
1 =
Clears IRQ interrupt request (clears IRQF).
0 =
No effect.
IRQF — IRQ Interrupt Request Flag
Writing to the IRQF ag bit will have no effect on it. If the additional setting of
IRQF ag bit is not cleared in the IRQ service routine and the IRQE enable bit
remains set the CPU will re-enter the IRQ interrupt sequence continuously until
either the IRQF ag bit or the IRQE enable bit is clear. The IRQF latch is
cleared by reset.
1 =
Indicates that an IRQ request is pending.
0 =
Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
pending. The IRQF ag bit can be cleared by writing a logic one to
the IRQR acknowledge bit to clear the IRQ latch and also
conditioning the external IRQ sources to be inactive (if the level
sensitive interrupts are enabled via mask option). Doing so before
exiting the service routine will mask out additional occurrences of
the IRQF.
IRQE — IRQ Interrupt Enable
The IRQE bit enables/disables the IRQF ag bit to initiate an IRQ interrupt
sequence.
1 =
Enables IRQ interrupt, that is, the IRQF ag bit can generate an
interrupt sequence. Reset sets the IRQE enable bit, thereby
enabling IRQ interrupts once the I-bit is cleared. Execution of the
STOP or WAIT instructions causes the IRQE bit to be set in order to
allow the external IRQ to exit these modes.
0 =
The IRQF ag bit cannot generate an interrupt sequence.
4.5.3 Port A External Interrupts (PA0-PA3, by mask option)
The IRQ interrupt can also be triggered by the inputs on the PA0 to PA3 port pins
if enabled by a single mask option. If enabled, the lower four bits of Port A can
activate the IRQ interrupt function, and the interrupt operation will be the same as
for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of these
input pins to be OR’ed with the input present on the IRQ pin. All PA0 to PA3 pins
must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt
sources are also controlled by the IRQE enable bit.
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