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參數資料
| 型號： | MC68HC05JB3JP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數： | 125/148頁 |
| 文件大?。?/td> | 1600K |
| 代理商： | MC68HC05JB3JP |
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GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
UNIVERSAL SERIAL BUS MODULE
MC68HC05JB3
10-10
REV 1
When using the remote wake-up capability, the rmware must wait for at least 5
ms after the bus is in the idle state before sending the remote wake-up resume
signaling. This allows the upstream devices to get into their suspend state and
prepare for propagating resume signaling. The FRESUM bit should be asserted to
cause the resume state on the USB data lines for at least 10ms, but not more than
15ms. Note that the resume signalling is controlled by the FRESUM bit and
meeting the timing specications is dependent on the rmware. When FRESUM is
cleared by rmware, the data lines will return to their high impedance state. Refer
to Section 10.5.5 for more information about how the Force Resume (FRESUM)
bit can be used to initiate the remote wake-up feature.
10.2.5 Low Speed Device
Externally, low speed devices are congured by the position of a pull-up resistor
on the USB D– pin of the MC68HC05JB3. Low speed devices are terminated as
shown in Figure 10-10 with the pull-up on the D– line.
Figure 10-10. External Low Speed Device Conguration
For low speed transmissions, the transmitter’s EOP width must be between
1.25
s and 1.50s. These ranges include timing variations due to differential
buffer delay and rise/fall time mismatches and to noise and other random effects.
A low speed receiver must accept a 670ns wide SE0 followed by a J transition as
a valid EOP. An SE0 narrower than 330ns or an SE0 not followed by a J transition
must be rejected as an EOP. An EOP between 330ns and 670ns may be rejected
or accepted as above. Any SE0 that is 2.5
s or wider is automatically a reset.
10.3
CLOCK REQUIREMENTS
The low speed data rate is nominally 1.5 Mbs. The OSCXCLK signal driven by the
oscillator circuits is the clock source for the USB module and requires that a 6
MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permitted
frequency tolerance for low speed functions is approximately
±1.5% (15000 ppm).
This tolerance includes inaccuracies from all sources: initial frequency accuracy,
crystal capacitive loading, supply voltage on the oscillator, temperature, and
aging. The jitter in the low speed data rate must be less than 10 ns. This tolerance
allows the use of resonators in low cost, low speed devices.
10.4
HARDWARE DESCRIPTION
The USB module as previously shown in Figure 10-1 contains four functional
blocks: a 3.3 volt regulator, a LS USB transceiver, the USB control logic, and the
USB registers. The following will detail the function of the regulator, transceiver
and control logic. See Section 10.5 for the register discussion.
1.5K
D+
D–
3.3V Regulator Out
USB Low Speed Cable
MC68HC05JB3
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