參數(shù)資料
型號: MC68HC05JB3JP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 135/148頁
文件大小: 1600K
代理商: MC68HC05JB3JP
November 5, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05JB3
UNIVERSAL SERIAL BUS MODULE
MOTOROLA
REV 1
10-19
10.5.1 USB Address Register (UADDR)
USBEN — USB Module Enable
This read/write bit enables and disables the USB module and the USB pins.
When USBEN is clear, the USB module will not respond to any tokens. Reset
clears this bit.
1 =
USB function enabled.
0 =
USB function disabled.
UADD6-UADD0 — USB Function Address
These bits specify the USB address of the device. Reset clears these bits.
10.5.2 USB Interrupt Register 0 (UIR0)
TXD0F — Endpoint 0 Data Transmit Flag
This read only bit is set after the data stored in Endpoint 0 transmit buffers has
been sent and an ACK handshake packet from the host is received. Once the
next set of data is ready in the transmit buffers, software must clear this ag by
writing a logic 1 to the TXD0FR bit. To enable the next data packet transmis-
sion, TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake will
be returned in the next IN transaction.
Reset clears this bit. Writing a logic 0 to TXD0F has no effect.
1 =
Transmit on Endpoint 0 has occurred.
0 =
Transmit on Endpoint 0 has not occurred.
RXD0F — Endpoint 0 Data Receive Flag
This read only bit is set after the USB module has received a data packet and
responded with an ACK handshake packet. Software must clear this ag by
writing a logic 1 to the RXD0FR bit after all of the received data has been read.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UADDR
R
USBEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
$0038
W
reset:
00000000
Figure 10-20. USB Address Register (UADDR)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UIR0
R
TXD0F
RXD0F
RSTF
SUSPND
TXD0IE
RXD0IE
00
$0039
W
TXD0FR
RXD0FR
reset:
00000000
= Unimplemented
Figure 10-21. USB Interrupt Register 0 (UIR0)
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