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參數(shù)資料
| 型號： | MC68HC05J5CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 46/69頁 |
| 文件大小： | 394K |
| 代理商： | MC68HC05J5CDW |
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GENERAL RELEASE SPECIFICATION
December 11, 1996
MOTOROLA
MULTI-FUNCTION TIMER
MC68HC05J5
8-2
REV 1.1
interrupt at the rate of fop/1024. Two additional stages produce the POR function
at fop/4064. The Timer Counter Bypass circuitry (available only in Expanded Test
Mode) is at this point in the timer chain. This circuit is followed by two more
stages, with the resulting clock (fop/16384) driving the Real Time Interrupt circuit.
The RTI circuit consists of three divider stages with a 1 of 4 selector. The output of
the RTI circuit is further divided by eight to drive the optional COP Watchdog
Timer circuit, which can be enabled by a mask option. The RTI rate selector bits,
and the RTI and TOF enable bits and ags are located in the Timer Control and
Status Register at location $08.
The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4 selec-
tor. The clock frequency that drives the RTI circuit is fop/2
14 (or f
op/16384) with
three additional divider stages giving a maximum interrupt period of fop/2
17 (or f
op/
131072).
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 4064 cycles, the power-on reset circuit is released which again
clears the counter chain and allows the device to come out of reset. At this point, if
RESET is not asserted, the timer will start counting up from zero and normal
device operation will begin. If RESET is asserted at any time during operation the
counter chain will be cleared.
8.1
TIMER REGISTERS
The 15-stage Multi-function Timer contains two registers: a Timer Counter Regis-
ter and a Timer Control/Status Register.
8.1.1 Timer Counter Register (TCR), $09
The Timer Counter Register is a read-only register which contains the current
value of the 8-bit ripple counter at the beginning of the timer chain. This counter is
clocked at fop divided by 4 and can be used for various functions including a soft-
ware input capture. Extended time periods can be attained using the TOF function
to increment a temporary RAM storage location thereby simulating a 16-bit (or
more) counter. The value of each bit of the TCR is shown in Figure 8-2. This reg-
ister is cleared by reset.
Figure 8-2. Timer Counter Register
TCR
$09
0
7
W
R
0000000
Reset
6543210
TMR0
TMR2
TMR1
TMR3
TMR4
TMR5
TMR6
TMR7
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