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參數(shù)資料
| 型號： | MC68HC05J5CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 29/69頁 |
| 文件大小： | 394K |
| 代理商： | MC68HC05J5CDW |
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December 11, 1996
GENERAL RELEASE SPECIFICATION
MC68HC05J5
MODES OF OPERATION
MOTOROLA
REV 1.1
6-1
SECTION 6
MODES OF OPERATION
The MC68HC05J5 has the following operating modes: Single-Chip Mode (SCM)
and self-check mode.
The Single-Chip Mode allows maximum use of pins for on-chip peripheral func-
tions.
The self-check mode capability of the MC68HC05J5 provides an internal check to
determine if the device is functional.
This section also provides a description of the low-power modes.
6.1
MODE ENTRY
The mode entry is done at the rising edge of the RESET pin. Once the device
enters one of the operating modes, the mode can be changed only by external
reset not software.
At the rising edge of the RESET pin, the device latches the states of the IRQ and
PB0 pins and places itself in the specied mode. While the RESET pin low, all
pins are congured as Single-Chip Mode. Table 6-1 shows the states of IRQ and
PB0 pins for each mode.
Table 6-1. Mode Select Summary
6.2
SINGLE-CHIP MODE (SCM)
The Single-Chip Mode allows the MCU to function as a self-contained microcon-
troller, with maximum use of the pins for on-chip peripheral functions.
In the Single-Chip Mode all address and data activity occurs within the MCU and
is not available externally. Single-Chip Mode is entered if the IRQ pin is within the
normal operating voltage range when the rising edge of a RESET or a COP
Watchdog reset or an internal LVR reset occurs. In Single-Chip Mode, all I/O port
pins are available.
Mode
RESET
IRQ
PB0
Single-Chip Mode
L or H
X
Self-Check Mode
VTST
H
VTST=1.8xVDD
H = VDD
L = GND
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