參數(shù)資料
型號: MC68HC05E6MDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 81/140頁
文件大?。?/td> 1141K
代理商: MC68HC05E6MDWR2
MC68HC05E6 — Rev. 1.0
MOTOROLA
Core Timer
45
Core Timer
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Real time interrupts (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Core timer registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Core timer during WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Core timer during STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
The MC68HC05E6 has a 15-stage ripple counter called the core timer
(CTIMER). Features of this timer are: timer overflow, power-on reset
(POR), real time interrupt (RTI) with four selectable interrupt rates, and
a computer operating properly (COP) watchdog timer.
As shown in Figure 10, the timer is driven by the internal bus clock
divided by four with a fixed prescaler. This signal drives an 8-bit ripple
counter. The value of this 8-bit ripple counter can be read by the CPU at
any time, by accessing the CTIMER counter register (CTCR) at address
$09. A timer overflow function is implemented on the last stage of this
counter, giving a possible interrupt at the rate of fOP/1024. (The POR
signal (tPORL) is also derived from this register, at fOP/4064.) The
counter register circuit is followed by four more stages, with the resulting
clock (fOP/16384) driving the real time interrupt circuit. The RTI circuit
consists of three divider stages with a 1-of-4 selector. The output of the
RTI circuit is further divided by eight to drive the COP watchdog timer
circuit. The RTI rate selector bits, and the RTI and CTIMER overflow
enable bits and flags, are located in the CTIMER control and status
register (CTCSR) at location $08.
1-ctimer
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