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參數(shù)資料
| 型號： | MC68HC05E0 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 73/96頁 |
| 文件大?。?/td> | 970K |
| 代理商： | MC68HC05E0 |
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8
MC68HC05E0
MOTOROLA
8-9
SERIAL INTERFACE
IRQACK — Interrupt Acknowledge Flag Bit
This bit is the serial interface interrupt ag, raised at the end of every SPI/I2C-bus transaction.
Writing a zero to IRQACK clears the interrupt ag, resets the interrupt circuitry and permits new
data to be written to the data register or newly received data to overwrite the old data in the
reception register (meaning the data register has already been read).
1 (set)
–
I2C-bus transaction completed
0 (clear) –
No I2C-bus transaction has occurred
NMA — No Master Acknowledge Bit
When set high NMA prevents the MC68HC05E0 from giving an acknowledge signal to a
peripheral after receiving a byte of data. An acknowledge is made if NMA is low.
1 (set)
–
Prevent acknowledgement after data receive
0 (clear) –
Permit acknowledgement after data receive
SP — STOP Bit
If high, an I2C-bus STOP condition is generated on the SDA line at the end of the next bus transfer.
If low, no STOP bit is produced.
1 (set)
–
Generate STOP condition after data transfer
0 (clear) –
Do not generate STOP condition after data transfer
ST — START Bit
If high, an I2C-bus START condition is generated on the SDA line at the beginning of the next bus
transfer. If low, no START bit is produced.
1 (set)
–
Generate START condition before data transfer
0 (clear) –
Do not generate START condition before data transfer
R/WB — Read/Write Bit
This bit selects the direction of the data transfer during SPI or I2C-bus operation.
1 (set)
–
Read (from peripheral)
0 (clear) –
Write (to peripheral)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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