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參數(shù)資料
| 型號(hào)： | MC68HC05E0 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 59/96頁(yè) |
| 文件大?。?/td> | 970K |
| 代理商： | MC68HC05E0 |
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7
MOTOROLA
7-2
MC68HC05E0
TIMERS
The maximum bus clock frequency (P02) is 4 MHz. One of four different sub-system clock
frequencies can be selected via bits 6 and 7 (SC0 and SC1) of the Timer Control Register ($000C)
(see Table 7-1).
A Timer Stop signal on the active low TS pin allows Timer A and Timer B to be halted. TS can be
used as a gate input to the two timers, thereby allowing pulse width measurement to be carried
out on the input signal. Halting the timers is also useful during emulation of the device and during
software debug. The SPI/I2C functions are not interrupted by the TS signal.
7.2
Timer A
Timer A consists of an 8-bit prescaler driving a 6-bit free-running counter (see Figure 7-2).
Table 7-1 Sub-system Clock Frequency Selection
SC1
SC0
Sub-system clock frequency (fSUB)
0
P02
÷8
0
1
P02
÷4
1
0
P02
÷2
1
P02
÷1
Figure 7-2 Timer A Structure
CETA
8 Bit
6 Bit
Timer A
Prescaler Register
INTMA
INTFA
INT2
(16
s - 32 ms)
Sub-system
Clock
Frequency
OF
(freerunning)
$000A
62
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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