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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 60/114頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MC68HC05CJ4FB |
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MOTOROLA
MC68HC(7)05CJ4
vi
Rev. 2.1
TABLE OF CONTENTS
Paragraph
Title
Page
10.2.6
Stop Condition ...................................................................................... 10-3
10.2.7
General Call Address Detect ................................................................ 10-3
10.3
Slave M-Bus Control Register (MBCR) ....................................................... 10-4
10.4
Slave M-Bus Status Register (MBSR) ........................................................ 10-6
10.5
M-Bus Address/Data Register (MBADR) .................................................... 10-7
10.6
Hardware Flowchart of the SOMB .............................................................. 10-8
10.7
SOMB Timing Diagrams ........................................................................... 10-10
SECTION 11
TIMER 1
11.1
Introduction ................................................................................................. 11-1
11.2
Counter ....................................................................................................... 11-2
11.3
Output Compare Register ........................................................................... 11-3
11.4
Input Capture Register ................................................................................ 11-4
11.5
Timer 1 Control Register (T1CR) ................................................................ 11-6
11.6
Timer 1 Status Register (T1SR) .................................................................. 11-7
11.7
Timer 1 During Wait Mode .......................................................................... 11-8
11.8
Timer 1 During Stop Mode .......................................................................... 11-8
SECTION 12
TIMER 2
12.1
Introduction ................................................................................................. 12-1
12.2
Flag Clearing Considerations ...................................................................... 12-2
12.2.1
Clearing Timer Overflow Flag (TOF) .................................................... 12-3
12.2.2
Clearing Timer Overflow Flag Enable (TOFE) ...................................... 12-3
12.3
Timer 2 Control and Status Register (T2CSR) ........................................... 12-4
12.4
COP Watchdog Reset ................................................................................. 12-6
12.5
Timer 2 Counter Register (T2CR) ............................................................... 12-6
12.6
Timer 2 During Wait Mode .......................................................................... 12-6
12.7
Timer 2 During Stop Mode .......................................................................... 12-6
SECTION 13
INSTRUCTION SET
13.1
Introduction ................................................................................................. 13-1
13.2
Addressing Modes ...................................................................................... 13-1
13.2.1
Inherent ................................................................................................ 13-1
13.2.2
Immediate ............................................................................................. 13-1
13.2.3
Direct .................................................................................................... 13-2
13.2.4
Extended .............................................................................................. 13-2
13.2.5
Indexed, No Offset ................................................................................ 13-2
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