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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 102/114頁 |
| 文件大小： | 361K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
MOTOROLA
TIMER 2
MC68HC(7)05CJ4
12-4
Rev. 2.1
1
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12.3 Timer 2 Control and Status Register (T2CSR)
The T2CSR contains the timer interrupt flag, the timer interrupt enable bits, and the
real time interrupt rate select bits.
TOF — Timer Over Flow
TOF is a clearable, read-only status bit and is set when the 8-bit ripple counter
rolls over from $FF to $00. A CPU interrupt request will be generated if TOFE is
set. Clearing the TOF is done by writing a zero to it (TOFR). Writing a one to
TOFR has no effect on the bit’s value. Reset clears TOF.
RTIF — Real Time Interrupt Flag
The real time interrupt circuit consists of a three stage divider and a 1 of 4
selector. The clock frequency that drives the RTI circuit is E/2**14 (or E/16384)
with three additional divider stages giving a maximum interrupt period of 65.5
milliseconds at a bus rate of 2 MHz. RTIF is a clearable, read-only status bit and
is set when the output of the chosen (1 of 4 selection) stage goes active. A CPU
interrupt request will be generated if RTIE is set. Clearing the RTIF is done by
writing a zero to it (RTIFR). Writing a one to RTIFR has no effect on this bit.
Reset clears RTIF.
NOTE
Care should be taken when clearing TOF and RTIF. Writing a zero to
a bit that is already clear can cause a pending interrupt to be missed.
For this reason, the use of a read-modify-write instruction is not
recommended. To insure proper operation, only write a logic zero to
a flag that is already set and a logic one to any flag that is clear.
TOFE — Timer Over Flow Enable
When this bit is set, a CPU interrupt request is generated when the TOF bit is
set. Reset clears this bit.
Bit 7
654321
Bit 0
$0013
T1SR
Read:
TOF
RTIF
TOFE
RTIE
COPE
IRQS
RT1
RT0
Write:
TOFR
RTIFR
Reset:
00000011
Figure 12-2. Timer 2 Control/Status Register
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