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參數(shù)資料
| 型號： | MC68HC05C5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 9/58頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MC68HC05C5P |
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Page 11
Section 3: Memory
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
3.1
ROM
The user ROM consists of 48 bytes of page zero ROM from $0020 to $004F, 5120 bytes
of ROM from $0A80 to $1E7F and 16 bytes of user vectors from $1FF0 to $1FFF. The
Self-Check ROM and vectors are located from $1E80 to $1FEF.
Eight of the user vectors, $1FF8 through $1FFF, are dedicated to reset and interrupt
vectors. The remaining eight locations, $1FF0 through $1FF7, are general purpose user
ROM locations.
3.2
RAM
The user RAM consists of 176 bytes of a shared stack area. The stack begins at address
$00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0. See
4.1.4 STACK POINTER (SP).
NOTE:
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
3.3
EEPROM
The EEPROM on this device is 128 bytes long and is located at address $0100.
Programming the EEPROM can be done by the user on a single byte basis by
manipulating the Programming Register, located at address $001C.
3.3.1
PROGRAMMING REGISTER $1C
The contents and use of the programming register are discussed below. This device
includes low-voltage programming inhibit (LVPI) circuitry which inhibits the use of the
programming register when the supply voltage (V
DD
) falls below V
LVPI
.
3.3.1.1
LVPI - Low-Voltage Programming Inhibit
LVPI is automatically set and cleared by the LVPI circuit and is not writable. The bit is set
when V
DD
falls below V
LVPI
and is cleared when V
DD
is above V
LVPR
. Note that the
V
DD
rise and fall slew rates (t
VDDR
and t
VDDF
) must be within the specification for
proper LVPI operation. If the specification is not met, the circuit will operate properly
LVPI
0
ER1
ER0
LATCH
EERC
EEPGM
CPEN
$1C
0
000000
0
RESET:
Figure 3-3: : Programming Register
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