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參數(shù)資料
| 型號： | MC68HC05C5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 25/58頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MC68HC05C5P |
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Page 25
Section 4: CPU Core
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
Table 4-1: Vector Address for Interrupts and Reset
4.5.1
HARDWARE CONTROLLED INTERRUPT SEQUENCE
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense
interrupts; however, they are acted upon in a similar manner. Flowcharts for hardware
interrupts are shown in Figure 4-4, and for STOP and WAIT in Figure 4-6. A discussion
is provided below.
1. RESET - A low input on the RESET input pin causes the program to
vector to its starting address which is specified by the contents of
memory locations $1FFE and $1FFF. The I bit in the condition code
register is also set. Much of the MCU is configured to a known state
during this type of reset as previously described in 4.4 RESETS.
2. STOP - The STOP instruction causes the oscillator to be turned off and
the processor to "sleep" until and external interrupt (IRQ) or reset
occurs.
3. WAIT - The WAIT instruction causes all processor clocks to stop, but
leaves the timer clock running. This "rest" state of the processor can be
cleared by reset, an external interrupt IRQ), or timer interrupt. There are
no special wait vectors for these individual interrupts.
4.5.2
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt: It is executed
regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI
executes after interrupts which were pending when the SWI was fetched, but before
interrupts generated after the SWI was fetched. The interrupt service routine address is
specified by the contents of memory locations $1FFC and $1FFD.
4.5.3
EXTERNAL INTERRUPT
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and
external) are disabled. Clearing the I bit enables interrupts. The interrupt request is
latched immediately following the falling edge of IRQ. It is then synchronized internally
and serviced as specified by the contents of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger is
available as a mask option.
Register
N/A
TSR
Flag
Name
N/A
ICF
OCF
TOF
Interrupts
Reset
Software
External Interrupt
Timer Input Capture
Timer Output Compare
Timer Overflow
CPU
Interrupt
RESET
SWI
IRQ
TIMER
Vector Address
$1FFE-$1FFF
$1FFC-$1FFD
$1FFA-$1FFB
$1FF8-$1FF9
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