參數(shù)資料
型號: MC68HC05C5P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: DIP-40
文件頁數(shù): 44/58頁
文件大小: 166K
代理商: MC68HC05C5P
Page 43
Section 8: Computer Operating Properly
MOTOROLA
MC68HC05C5 Specification Rev. 1.2
SECTION 8
COMPUTER OPERATING PROPERLY
8.1
INTRODUCTION
This device includes a "Watchdog" Computer Operating Properly (COP) feature as a
mask option. The COP is implemented with an 18-bit ripple counter. This provides a
timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP should timeout, a
system reset will occur and the device will be re-initialized in the same fashion as a POR
or external reset.
8.2
RESETTING THE COP
Preventing a COP reset is done by writing a "0" to the COPF bit. This action will reset the
counter and begin the timeout period again. The COPF bit is bit 0 of address $1FF0. A
read of address $1FF0 will result in the user defined ROM data at that location.
8.3
COP TEST FEATURES
For speeding up the COP test, a feature was added in the Self-Check mode to split the
18-bit counter into 6-bit and 12-bit counters clocked in parallel where the output of the 6-
bit counter drives the COP logic. Splitting the counter is accomplished by writing a "1" to
bit 7 of $1FF0. Writing a "0" to bit 7 of $1FF0 will reconnect the two halves of the COP
counter.
8.4
COP DURING WAIT MODE
The COP will continue to operate normally during WAIT mode. The software should pull
the device out of WAIT mode periodically and reset the COP by writing to the COPF bit to
prevent a COP reset.
8.5
COP DURING STOP MODE
STOP mode disables the oscillator circuit and thereby turns the clock off for the entire
device. The COP counter will be reset when STOP mode is entered. If a reset is used to
exit STOP mode, the COP counter will be reset after the 4064 cycles of delay after STOP
mode. If an IRQ is used to exit STOP mode, the COP counter will not be reset after the
4064-cycle delay and will have that many cycles already counted when control is returned
to the program.
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