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| 型號(hào)： | MC68HC000CEI16R |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 7/189頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 16MHZ 64-PLCC |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 16MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（25x25） |
| 包裝： | 帶卷 (TR) |
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MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL
6- 19
shown in Figure 6-9. If the bus cycle is a read, the data at the fault address should be
written to the images of the data input buffer, instruction input buffer, or both according to
the data fetch (DF) and instruction fetch (IF) bits.* In addition, for read-modify-write cycles,
the status register image must be properly set to reflect the read data if the fault occurred
during the read portion of the cycle and the write operation (i.e., setting the most
significant bit of the memory location) must also be performed. These operations are
required because the entire read-modify-write cycle is assumed to have been completed
by software. Once the cycle has been completed by software, the rerun (RR) bit in the
special status word is set to indicate to the processor that it should not rerun the cycle
when the RTE instruction is executed. If the RR bit is set when an RTE instruction
executes, the MC68010 reads all the information from the stack, as usual.
15
14
13
12
11
10
9
8
7
3
2
0
RR
*
I F
DF
RM
HB
BY
RW
*
FC2–FC0
RR — Rerun flag; 0=processor rerun (default), 1=software rerun
IF
— Instruction fetch to the instruction input buffer
DF — Data fetch to the data input buffer
RM — Read-modify-write cycle
HB — High-byte transfer from the data output buffer or to the data input buffer
BY — Byte-transfer flag; HB selects the high or low byte of the transfer register. If BY is clear, the transfer is word.
RW
—
Read/write flag; 0=write, 1=read
FC — The function code used during the faulted access
*
— These bits are reserved for future use by Motorola and will be zero when written by the MC68010.
Figure 6-9. Special Status Word Format
6.3.10 Address Error
An address error exception occurs when the processor attempts to access a word or long-
word operand or an instruction at an odd address. An address error is similar to an
internally generated bus error. The bus cycle is aborted, and the processor ceases current
processing and begins exception processing. The exception processing sequence is the
same as that for a bus error, including the information to be stacked, except that the
vector number refers to the address error vector. Likewise, if an address error occurs
during the exception processing for a bus error, address error, or reset, the processor is
halted.
On the MC68010, the address error exception stacks the same information stacked by a
bus error exception. Therefore, the RTE instruction can be used to continue execution of
the suspended instruction. However, if the RR flag is not set, the fault address is used
when the cycle is retried, and another address error exception occurs. Therefore, the user
must be certain that the proper corrections have been made to the stack image and user
registers before attempting to continue the instruction. With proper software handling, the
address error exception handler could emulate word or long-word accesses to odd
addresses if desired.
*If the faulted access was a byte operation, the data should be moved from or to the least significant byte of
the data output or input buffer images, unless the high-byte transfer (HB) bit is set. This condition occurs if a
MOVEP instruction caused the fault during transfer of bits 8–15 of a word or long word or bits 24–31 of a
long word.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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