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| 型號： | MC68HC000CEI16R |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 188/189頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 16MHZ 64-PLCC |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 16MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（25x25） |
| 包裝： | 帶卷 (TR) |
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MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL
6- 13
register on the supervisor stack. The offset value in the format/offset word on the
MC68010 is the vector number multiplied by four. The format is all zeros. The saved value
of the program counter is the address of the instruction that would have been executed
had the interrupt not been taken. The appropriate interrupt vector is fetched and loaded
into the program counter, and normal instruction execution commences in the interrupt
handling routine. Priority level 7 is a special case. Level 7 interrupts cannot be inhibited by
the interrupt priority mask, thus providing a "nonmaskable interrupt" capability. An interrupt
is generated each time the interrupt request level changes from some lower level to level
7. A level 7 interrupt may still be caused by the level comparison if the request level is a 7
and the processor priority is set to a lower level by an instruction.
6.3.3 Uninitialized Interrupt
An interrupting device provides an M68000 interrupt vector number and asserts data
transfer acknowledge (DTACK), or asserts valid peripheral address (VPA), or auto vector
(AVEC), or bus error (BERR) during an interrupt acknowledge cycle by the MC68000. If
the vector register has not been initialized, the responding M68000 Family peripheral
provides vector number 15, the uninitialized interrupt vector. This response conforms to a
uniform way to recover from a programming error.
6.3.4 Spurious Interrupt
During the interrupt acknowledge cycle, if no device responds by asserting DTACK or
AVEC, VPA, BERR should be asserted to terminate the vector acquisition. The processor
separates the processing of this error from bus error by forming a short format exception
stack and fetching the spurious interrupt vector instead of the bus error vector. The
processor then proceeds with the usual exception processing.
6.3.5 Instruction Traps
Traps are exceptions caused by instructions; they occur when a processor recognizes an
abnormal condition during instruction execution or when an instruction is executed that
normally traps during execution.
Exception processing for traps is straightforward. The status register is copied; the
supervisor mode is entered; and tracing is turned off. The vector number is internally
generated; for the TRAP instruction, part of the vector number comes from the instruction
itself. The format/offset word (MC68010 only), the program counter, and the copy of the
status register are saved on the supervisor stack. The offset value in the format/offset
word on the MC68010 is the vector number multiplied by four. The saved value of the
program counter is the address of the instruction following the instruction that generated
the trap. Finally, instruction execution commences at the address in the exception vector.
Some instructions are used specifically to generate traps. The TRAP instruction always
forces an exception and is useful for implementing system calls for user programs. The
TRAPV and CHK instructions force an exception if the user program detects a run-time
error, which may be an arithmetic overflow or a subscript out of bounds.
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For More Information On This Product,
Go to: www.freescale.com
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