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| 型號： | MC68HC000CEI16R |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/189頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 16MHZ 64-PLCC |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 16MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（25x25） |
| 包裝： | 帶卷 (TR) |
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MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL
6- 15
6.3.7 Privilege Violations
To provide system security, various instructions are privileged. An attempt to execute one
of the privileged instructions while in the user mode causes an exception. The privileged
instructions are as follows:
AND Immediate to SR
MOVE USP
EOR Immediate to SR
OR Immediate to SR
MOVE to SR (68010 only)
RESET
MOVE from SR (68010 only)
RTE
MOVEC (68010 only)
STOP
MOVES (68010 only)
Exception processing for privilege violations is nearly identical to that for illegal
instructions. After the instruction is fetched and decoded and the processor determines
that a privilege violation is being attempted, the processor starts exception processing.
The status register is copied; the supervisor mode is entered; and tracing is turned off.
The vector number is generated to reference the privilege violation vector, and the current
program counter and the copy of the status register are saved on the supervisor stack. If
the processor is an MC68010, the format/offset word is also saved. The saved value of
the program counter is the address of the first word of the instruction causing the privilege
violation. Finally, instruction execution commences at the address in the privilege violation
exception vector.
6.3.8 Tracing
To aid in program development, the M68000 Family includes a facility to allow tracing
following each instruction. When tracing is enabled, an exception is forced after each
instruction is executed. Thus, a debugging program can monitor the execution of the
program under test.
The trace facility is controlled by the T bit in the supervisor portion of the status register. If
the T bit is cleared (off), tracing is disabled and instruction execution proceeds from
instruction to instruction as normal. If the T bit is set (on) at the beginning of the execution
of an instruction, a trace exception is generated after the instruction is completed. If the
instruction is not executed because an interrupt is taken or because the instruction is
illegal or privileged, the trace exception does not occur. The trace exception also does not
occur if the instruction is aborted by a reset, bus error, or address error exception. If the
instruction is executed and an interrupt is pending on completion, the trace exception is
processed before the interrupt exception. During the execution of the instruction, if an
exception is forced by that instruction, the exception processing for the instruction
exception occurs before that of the trace exception.
As an extreme illustration of these rules, consider the arrival of an interrupt during the
execution of a TRAP instruction while tracing is enabled. First, the trap exception is
processed, then the trace exception, and finally the interrupt exception. Instruction
execution resumes in the interrupt handler routine.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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