MC68F375
CDR MoneT FLASH FOR THE IMB3 (CMFI)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
10-16
10.4.6 High Voltage Control Register
The high voltage control register is used to control the program and erase operations
of the CMFI array.
CMFICTL1 — CMFI High Voltage Control Register 1
0xYF F80C
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
HVS
0
SCLKR1
NOTES:
1. These fields are NOT locked by SES if the value of the PAWS bits (in CMFITST) is not 0b000.
0
CLKPE1
0
CLKPM1
RESET:
0
U2
2. The default state of these bits will be read from the shadow row location 0xC on reset.
—
U2
—
U2
Table 10-9 CMFICTL1 Bit Settings
Bit(s)
Name
Description
15
HVS
High voltage status. The HVS bit is for status only and writes will have no effect. During a pro-
gram or erase pulse this bit will be a 1 while the pulse is active or during recovery. The BIU will
not acknowledge (IAACKB not asserted) an access to an array location if HVS = 1. While HVS
= 1 SES cannot be changed and the CMFI cannot enter low power clock stop operation. The
program or erase pulse becomes active by setting the EHV bit and is terminated by clearing EHV
or by the pulse width timing control.
The recovery time is the time that the CMFI EEPROM requires to remove the program or erase
voltage from the array or shadow information before switching to another mode of operation. The
recovery time is determined by the system clock range (SCLKR[0:2]) and the PE bit. The recov-
ery time is 48 of the scaled clock periods unless SCLKR = 0 then the recovery time is 128 clocks.
Once master reset is completed HVS shall indicate no program or erase pulse (HVS = 0).
0 = Program or erase pulse is not applied to the CMFI.
1 = Program or erase pulse is applied to the CMFI.
14
—
Reserved
13:11
SCLKR
System clock range. The SCLKR bits are write protected by the SES bit. Writes to CMFICTL will
not change SCLKR if SES = 1. The first term of the timing control is the clock scaling, R. The
value of R is determined by the system clock range (SCLKR). SCLKR defines the pulse timer’s
base clock using the system clock. The following table should be used to set SCLKR based upon
the system clock frequency. The system clock period is multiplied by the clock scaling value to
generate a 83. 3 ns to 125 ns scaled clock. This scaled clock is used to run the charge pump
submodule and the next functional block of the timing control.
10
—
Reserved
9:8
CLKPE
Clock period exponent. The CLKPE[1:0] bits are write protected by the SES bit. Writes to
CMFICTL will not change CLKPE[1:0] if SES = 1. The second term of the timing control is the
exponential clock multiplier, N. The program pulse number (pulse), clock period exponent
(CLKPE[1:0]) CSC, and PE define the exponent in the 2N multiply of the clock period. The expo-
nent, N, is defined by the equation:
N = 5 + CLKPE[1:0] + (PE 10)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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