參數(shù)資料
型號： MC68EN302CPV20BT
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù)： 69/128頁
文件大?。?/td> 641K
代理商： MC68EN302CPV20BT
ETHERNET Controller
4-6
MC68EN302 REFERENCE MANUAL
MOTOROLA
4.1.4 INTERRUPT VECTOR REGISTER (IVEC)
The IVEC register controls the interrupt vector generated by the Ethernet controller during
an interrupt acknowledge cycle. This register can only be written when the ETHER_EN bit
in the ECNTRL register is cleared. This register is reset to $000F.
15–8—Reserved.
Should be written to zero by the host processor. These bits are always read as zero.
VG—Vector Granularity.
0 = The interrupt vector is not modified to reflect the cause of the interrupt.
1 = The interrupt vector is modified to indicate the cause of the interrupt, replacing the
lower two bits of the interrupt vector according to the following table:
If multiple interrupt sources are present simultaneously and VG = 1, the INV bits will be set
based on the following priority (highest ot lowest);
1. Time critical interrupt.
2. Receive interrupt
3. Transmit interrupt
4. Non-time critical interrupt.
For example, if both RXB and TFINT interrupts are asserted, INV1–INV0 will equal 00.
Interrupt Vector1–0 represent the values of the two lower bits placed on the data bus during
an interrupt acknowledge cycle. VG is cleared by reset.
INV7–0—Interrupt Vector.
INV is the eight bit vector that the Ethernet controller places on the low byte of the data bus
during an interrupt acknowledge cycle.
4.1.5 INTERRUPT EVENT REGISTER (INTR_EVENT)
When an event occurs that sets a bit in the Interrupt Event Register, and the corresponding
bit in the interrupt mask register (INTR_MASK) is set, an interrupt will be generated. To clear
15
14
13
12
11
10
9876543210
00000000
INV<7:0>
INTERRUPT VECTOR1–0
CAUSE
EXAMPLES
00
Receive Interrupt
RFINT, RXB
01
Transmit Interrupt
TFINT, TXB
10
Non-Time Critical Interrupt
HBERR, BABR, BABT, GRA, BOD, EBERR
11
Time Critical Interrupt
BSY
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