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| 型號： | MC68360UMAD |
| 廠商： | Motorola, Inc. |
| 英文描述： | Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1 |
| 中文描述： | 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 159K |
| 代理商： | MC68360UMAD |
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16
MC68360 USER’S MANUAL ERRATA
MOTOROLA
2. Inconsistent text in Clocking strategy.
On page 9-3, section 9.1.1.2. The paragraph describes the clocking strategy using a
32.768KHz crystal where the Figure 9-1 shows a 25MHz crystal oscillator set up.
To be consistent the following text should replace the text of section 9.1.1.2.
9.1.1.2 Clocking Strategy.
In this application, the system clock is generated from a 25MHz crystal oscillator
output into the QUICC. The QUICC's internal phase-locked loop (PLL) locks to
the input, multiplies the frequency by one, and uses the 25 MHz as the result sys-
tem frequency. The PLL also multiply the clock by two and outputs a 50 MHz sig-
nal on CLKO2. Neither CLKO pin is required for the application. It is
recommended that the CLKO outputs be disabled in software to save power.
The use of a 25MHz crystal oscillator is not a requirement in the application. A
4-MHz crystal or a 32.768-kHz crystal could have been used, if desired. (See
section 6.5 for notes on crystal use.)
The QUICC clocking section allows for the clock oscillator to be kept running
through the VDDSYN pin in a power-down situation. This section does not
address low-power issues, however.
3. Typo on Configuring the Memory Controller.
On page 9-11, section 9.1.3.2, the first statement on page 9-12:
“NCS should normally be cleared”
This should be:
“NCS should normally be set”
4. Error in text.
On page 9-13, the first sentence “To configure the QUICC for 16 bit data bus...” Should be
replaced with “User should drive the 16BM pin when the QUICC is in reset. User should
NOT simply tie 16BM to RESETH/RESETS since PRTY3 and PRTY2 pins will be driven the
QUICC even though there are not applicable to the current bus size.
5. MC68040 Companion Mode Bus Cycle Note.
On page 9-31, section 9.4, add the following note:
NOTE
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關PDF資料 |
PDF描述 |
|---|---|
| MC68360CFE25 | QUad Integrated Communications Controller Users Manual |
| MC68360CRC25 | QUad Integrated Communications Controller Users Manual |
| MC68360FE25 | QUad Integrated Communications Controller Users Manual |
| MC68360FE25V | QUad Integrated Communications Controller Users Manual |
| MC68360FE33 | QUad Integrated Communications Controller Users Manual |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68360VR25L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25LR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25VL | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25VLR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR33L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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