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| 型號(hào)： | MC68332ACAG25 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 49/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 25MHZ 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 25MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 15 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
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MC68332
MOTOROLA
MC68332TS/D
53
5.1.2 Input Capture/Input Transition Counter (ITC)
Any channel of the TPU can capture the value of a specified TCR upon the occurrence of each transition
or specified number of transitions, and then generate an interrupt request to notify the CPU. A channel
can perform input captures continually, or a channel can detect a single transition or specified number
of transitions, then cease channel activity until reinitialization. After each transition or specified number
of transitions, the channel can generate a link to a sequential block of up to eight channels. The user
specifies a starting channel of the block and the number of channels within the block. The generation
of links depends on the mode of operation. In addition, after each transition or specified number of tran-
sitions, one byte of the parameter RAM (at an address specified by channel parameter) can be incre-
mented and used as a flag to notify another channel of a transition.
5.1.3 Output Compare (OC)
The output compare function generates a rising edge, falling edge, or a toggle of the previous edge in
one of three ways:
1.
Immediately upon CPU initiation, thereby generating a pulse with a length equal to a program-
mable delay time.
2.
At a programmable delay time from a user-specified time.
3.
Continuously. Upon receiving a link from a channel, OC references, without CPU interaction, a
specifiable period and calculates an offset:
Offset = Period
Ratio
where Ratio is a parameter supplied by the user.
This algorithm generates a 50% duty-cycle continuous square wave with each high/low time equal to
the calculated OFFSET. Due to offset calculation, there is an initial link time before continuous pulse
generation begins.
5.1.4 Pulse-Width Modulation (PWM)
The TPU can generate a pulse-width modulation waveform with any duty cycle from zero to 100% (with-
in the resolution and latency capability of the TPU). To define the PWM, the CPU provides one param-
eter that indicates the period and another parameter that indicates the high time. Updates to one or both
of these parameters can direct the waveform change to take effect immediately, or coherently beginning
at the next low-to-high transition of the pin.
5.1.5 Synchronized Pulse-Width Modulation (SPWM)
The TPU generates a PWM waveform in which the CPU can change the period and/or high time at any
time. When synchronized to a time function on a second channel, the synchronized PWM low-to-high
transitions have a time relationship to transitions on the second channel.
5.1.6 Period Measurement with Additional Transition Detect (PMA)
This function and the following function are used primarily in toothed-wheel speed-sensing applications,
such as monitoring rotational speed of an engine. The period measurement with additional transition
detect function allows for a special-purpose 23-bit period measurement. It can detect the occurrence of
an additional transition (caused by an extra tooth on the sensed wheel) indicated by a period measure-
ment that is less than a programmable ratio of the previous period measurement.
Once detected, this condition can be counted and compared to a programmable number of additional
transitions detected before TCR2 is reset to $FFFF. Alternatively, a byte at an address specified by a
channel parameter can be read and used as a flag. A nonzero value of the flag indicates that TCR2 is
to be reset to $FFFF once the next additional transition is detected.
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