參數(shù)資料
型號(hào): MC68332ACAG25
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 13/88頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 25MHZ 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: M683xx
核心處理器: CPU32
芯體尺寸: 32-位
速度: 25MHz
連通性: EBI/EMI,SCI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲(chǔ)器類型: ROMless
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
MOTOROLA
MC68332
20
MC68332TS/D
3.2.2 System Protection Control Register
The system protection control register controls system monitor functions, software watchdog clock
prescaling, and bus monitor timing. This register can be written only once following power-on or reset,
but can be read at any time.
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following ta-
ble gives the ratio for each combination of SWP and SWT bits.
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the following table.
SYPCR —System Protection Control Register
$YFFA21
15
8
7
6
5
4
3
2
1
0
NOT USED
SWE
SWP
SWT
HME
BME
BMT
RESET:
1
MODCLK
0
SWP
SWT
Ratio
000
29
001
211
010
213
011
215
100
218
101
220
110
222
111
224
BMT
Bus Monitor Time-out Period
00
64 System Clocks
01
32 System Clocks
10
16 System Clocks
11
8 System Clocks
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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