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| 型號(hào)： | MC68322FT25 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 25 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 286/293頁(yè) |
| 文件大?。?/td> | 1002K |
| 代理商： | MC68322FT25 |
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DMA Interface
MOTOROLA
MC68322 USER’S MANUAL
8-3
8.1.2 Transfer Count Fields
Each DMA configuration register provides a 14-bit programmable transfer count field, thus
allowing for a maximum 16-Kbyte or 16-Kword transfers. The transfer count is in words if the
selected DMA channel is programmed to perform word-sized transfers. Similarly, the
transfer count is in bytes if the DMA channel is programmed to perform byte-sized transfers.
Writing this register activates the DMA channel, so that all other configuration register fields
must be initialized before writing the transfer count field.
When activated, the transfer count value is loaded into an internal counter and decremented
after each destination transfer. The transfer count field is not double buffered, so writing a
new value during an active transfer will not start the next DMA operation at the conclusion
of the current operation. However, if a new value is written to the transfer count field during
an active transfer, the new value is ignored.
During an active transfer, reading the transfer count field will reflect the current value of the
destination transfer count. This value is required to determine the amount of data remaining
to be transferred when a DMA channel is shut down using flush request. To assure an
accurate value after issuing a flush request, the transfer count should be read only after
receiving a DMA complete interrupt event. This ensures that all data was transferred and is
reflected in the count value.
8.1.3 Flush Request (FR) Fields
Each DMA channel contains a write-only control field (FR) that allows the core real-time
control over an active DMA transfer. A read by the core results in a value of zero. The FR bit
(when set during an active transfer) shuts down the transfer and then returns the DMA
channel to a condition ready for a new operation. For transfers to DRAM, the FR bit instructs
the channel to disable reading source data and to finish transferring any data left in the
internal data latch to DRAM. For transfers from DRAM, the FR bit instructs the DMA channel
to disable reading source data and to discard any data left in the internal data latch that was
read from DRAM. When completed, a DMA complete interrupt is posted and the DMA
channel controllers return to the idle state.
8.2 GDMA CONTROL REGISTER
The GDMA control register (GDMCR) is used to configure the transfer direction, transfer
data width, and DREQ input mode, as well as enable CS
× during MC68322 bus cycles. This
register is not double buffered and writing a new value during an active transfer will change
the current operational mode of the GDMA channel. This is not recommended. When read
by the core, the register reflects the current programmed bit fields. Figure 8-2 illustrates the
GDMA control register.
Figure 8-2. GDMA Control Register
RESERVED
15
14
13
12
11
10
9
8
7
65
4
3
2
1
0
00FFF21C
D
DS
DM
W
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