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Introduction
1-6
MC68322 USER’S MANUAL
MOTOROLA
1.2.5 DRAM Controller
The MC68322 provides a fully integrated bursting DRAM controller containing six DRAM
banks of varying programmable sizes and locations. They can be located contiguously or
disjointedly, as required by the operating environment. The DRAM controller multiplexes
addresses to provide up to 8M of DRAM address space per bank. The timing parameters
for each DRAM bank are preprogrammed to provide a 3-, 4-, or 5-clock access from industry
standard fast-page mode DRAMs. On reset, all DRAM banks are disabled. Additionally, the
DRAM controller provides a separate 16-bit DRAM data path and a write enable signal for
a glueless DRAM interface. DRAM refresh cycles are carried out with CAS before RAS
refresh cycles. The DRAM refresh rate is fully programmable and the controller performs
refreshes from system reset until it is initialized.
1.2.6 DMA Interface
The DMA interface contains two DMA controllers—a single-ended general-purpose DMA
(GDMA) and a dedicated parallel port interface DMA (PDMA) controller. The DMA interface
can be programmed to transfer data from a high-speed I/O peripheral to DRAM with minimal
intervention from the core.
1.2.7 Parallel Port Interface
The MC68322 contains a direct, IEEE 1284 Level 2 compliant, bidirectional 8-bit PPI. The
PPI supports four IEEE 1284 communications modes—compatibility (Centronics), nibble,
byte, and enhanced capabilities port (ECP). It also fully supports all variants of these modes,
including device ID requests and run-length encoded data compression. The PPI contains
specialized hardware to provide automatic handshaking during forward data transfers.
When hardware handshaking is used in conjunction with the PDMA, transfer rates as high
as 2M/sec and up can be achieved in the ECP forward mode. The hardware handshaking
can also be completely disabled for the software to directly control the parallel port interface
signals and support new protocols. Control and data signals provide a glueless interface to
the parallel port.
1.3 INTERNAL MEMORY MAP
The MC68322 uses memory-mapped registers that occupy 4K of memory space. With these
registers the hardware configuration and timing can be set, the status information can be
read, and the PVC, RGP, DMA, and PPI interfaces can be controlled. All registers can be
written and read, except for a few read-only and write-only registers that are noted. For more
information about each register, see its corresponding module’s section. Appendix C
Memory-Mapped Register Summary discusses all the registers and their location in
memory during power-up.
Register operations are implemented within one MC68322 bus cycle for both read and write
operations and are completed without asserting any wait states. The registers should only
be read and/or written as 16-bit words. All register addresses are on word boundaries. The
MC68322 powers up with a 16M memory map with the registers occupying the upper 4K of
the 16M of memory space. They are located at address range 0x00FFF000 through
0x00FFFFFF. The MC68322 memory map for a 16M memory space is illustrated in
Figure 1-3.