參數(shù)資料
型號(hào): MC68307CFG16
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 127/264頁(yè)
文件大小: 949K
代理商: MC68307CFG16
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Applications Information
MOTOROLA
MC68307 USER’S MANUAL
10-5
10.1.2 EPROM Memory Interface
The BUSW0 signal is used to select either an 8- or 16-bit EPROM mode for boot-up after
reset. In this case BUSW0 is tied low, and a standard, low cost, 8-bit EPROM is used. The
EPROM interface is a straight connection of CS0, address and data. The 8 data lines are
connected on the upper half of the data bus (D15–D8).
CS0 is used to select the EPROM and enable its output for a specified address range. After
reset, the default CS0 programming is for the first 8 Kbytes address range, accessible with
6 wait states. The CS0 registers are usually reprogrammed as one of the first software activ-
ities, to set up the desired address space and wait state options.
Some processor systems need a read/write control signal to the EPROM output enable to
avoid data contention in the event of an accidental write to ROM. The MC68307 can avoid
this by programming CS0 to assert for read accesses only.
Note that with BUSW0 pulled high, the 16-bit EPROM interface using two 8-bit EPROMs is
equally simple. Both EPROMs are chip selected by CS0. The upper (even) byte EPROM is
output enabled by UDS, while the lower (odd) byte EPROM is output enabled by LDS. The
address lines used by two 27C010’s would be A17–A1.
10.1.3 RAM Memory Interface
The 16-bit RAM interface is controlled using CS1, UDS, LDS, R/W, address and data. CS1
is used to select RAM for read/write accesses within a programmed address range. It must
be software configured before any RAM accesses are possible. For example, stacking oper-
ations such as interrupt or exception handling, and subroutine branches are not possible
until CS1 is configured. In this instance, CS1 should be programmed as a 16-bit port, with
suitable address range, address space and wait states.
The UDS/LDS signals are used to qualify accesses to the upper/lower byte of the selected
RAM data word. The R/W dictates whether a RAM read or write takes place.
It simplifies the interface to output enable the RAMs each time they are chip selected.
Although, when using alternative RAMs, care should be taken that the RAMs do not drive
data out when output enabled during a write. Almost all RAMs including the MCM6206 can
do this.
Note that for an 8-bit RAM interface using an MC6206, CS1 could be connected to the chip
enable, UDS to the output enable, R/W to the read/write, A14–A0 to the address lines and
D15-D8 to the data bus. After reset, CS1 must be software configured for 8-bit mode.
10.1.4 RS232 UART Port
The MC68307’s UART signals (TxD, RxD, RTS, CTS) are connected to an MC145407
RS232 level driver. On the RS232 side, the UART signals are made available to a standard
RS232 connector. This creates a communication channel between the user and system. For
instance, a terminal (or terminal emulator) could control the system via a user preferred
debug monitor coded into the EPROM; this is an invaluable debug feature during the devel-
opment stages of a system design.
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