參數(shù)資料
型號: MC56F8345VFGE
廠商: Freescale Semiconductor
文件頁數(shù): 7/172頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 60MHZ 128-LQFP
標(biāo)準(zhǔn)包裝: 72
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 49
程序存儲(chǔ)器容量: 136KB(68K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 128-LQFP
包裝: 托盤
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8345 Technical Data, Rev. 17
104
Freescale Semiconductor
Preliminary
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
Reset sequencing
Clock generation & distribution
Stop/Wait control
Pull-up enables for selected peripherals
System status registers
Registers for software access to the JTAG ID of the chip
Enforcing Flash security
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory
Power-saving clock gating for peripheral
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be done
explicitly
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
Controls to enable/disable the 56800E core WAIT and STOP instructions
Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be 3 x 32
clocks (phased release of reset) for reset, except for POR, which is 221 clock cycles.
Controls reset sequencing after reset
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
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