參數(shù)資料
型號: MC56F8025VLD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù): 9/161頁
文件大小: 2160K
代理商: MC56F8025VLD
56F8035/56F8025 Data Sheet, Rev. 6
106
Freescale Semiconductor
Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2)
6.3.23.1
Reserved—Bits 15–13
This bit field is reserved. Each bit must be set to 0.
6.3.23.2
Select Input Source for TA3 (IPS2_TA3)—Bit 12
This field selects the alternate input source signal to feed Quad Timer A, input 3.
0 = I/O pin (External) - Use Timer A3 input/output pin
1 = PWM SYNC (Internal) - Use PWM reload synchronization signal
6.3.23.3
Reserved—Bits 11–9
This bit field is reserved. Each bit must be set to 0.
6.3.23.4
Select Input Source for TA2 (IPS2_TA2)—Bit 8
This field selects the alternate input source signal to feed Quad Timer A, input 2.
0 = I/O pin (External) - Use Timer A2 input/output pin
1 = CMPBO (Internal) - Use Comparator B output
6.3.23.5
Reserved—Bits 7–5
This bit field is reserved. Each bit must be set to 0.
6.3.23.6
Select Input Source for TA1 (IPS2_TA1)—Bit 4
This field selects the alternate input source signal to feed Quad Timer A, input 1.
0 = I/O pin (External) - Use Timer A1 input/output pin
1 = CMPAO (Internal) - Use Comparator A output
6.3.23.7
Reserved—Bits 3–0
This bit field is reserved. Each bit must be set to 0.
For Timer A to detect the PWM SYNC signal, the clock rate of both the PWM module and Timer A
module must be identical, at either the system clock rate or 3X system clock rate.
6.4 Clock Generation Overview
The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to
produce a system clock at a maximum of 32MHz for the peripheral, core, and memory. It divides the
Base + $1A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
IPS2_
TA3
0
IPS2_
TA2
0
IPS2_
TA1
0
Write
RESET
0
0000000
0000
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