參數(shù)資料
型號： MC56F8011VFAE
廠商： Freescale Semiconductor
文件頁數(shù)： 49/126頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTLR 32-LQFP
標(biāo)準(zhǔn)包裝： 250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 12KB（6K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
配用： CPA56F8013-ND - BOARD SOCKET FOR MC56F8013
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
Pin Descriptions
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
29
3.5 Pin Descriptions
3.5.1
External Reference (GPIOB6 / RXD / SDA / CLKIN)
After reset, the internal relaxation oscillator is selected as the clock source for the chip. The user then has
the option of switching to an external clock reference if desired by enabling the PRECS bit in the OCCS
Oscillator Control register.
Part 4 Memory Map
4.1 Introduction
The 56F8013/56F8011 device is a 16-bit motor-control chip based on the 56800E core. It uses a
Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is
used in both spaces and Flash memory is used only in Program space.
This section provides memory maps for:
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
4.2 Interrupt Vector Table
Table 4-2 provides the 56F8013/56F8011’s reset and interrupt priority structure, including on-chip
peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts
lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing
some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.5.6
for the reset value of the VBA.
By default, VBA = 0, and the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8013
56F8011
Use Restrictions
Program Flash
(PFLASH)
8k x 16
6k x 16
Erase / Program via Flash interface unit and word writes to CDBW
Unified RAM (ram)
2k x 16
1k x 16
Usable by both the Program and Data memory spaces
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MC56F8013 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
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