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參數(shù)資料
| 型號(hào)： | MC34982PNA |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 mOhm)(單智能大電流帶自保護(hù)功能的硅高端開關(guān)（2mOhm）) |
| 中文描述： | 單智能大電流的自我保護(hù)硅高邊開關(guān)（2.0毫歐）（單智能大電流帶自保護(hù)功能的硅高端開關(guān)（2mOhm）） |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 771K |
| 代理商： | MC34982PNA |
33982
20
Go to: www.freescale.com
Previous Address SOA[2:0]=100
The returned data contain the programmed values in the
DICR.
Previous Address SOA[2:0]=101
SOA3 = 0. The returned data contain the programmed
values in the OSDR. Bit OD3 (FSM_HS) reflects the state
of the output in the Fail-Safe mode after a watchdog
timeout occurs.
SOA3 = 1. The returned data contain the programmed
values in the WDR. Bit OD2 (WDTO) reflects the status of
the watchdog circuitry. If WDTO bit is [1], the watchdog
has timed out and the device is in Fail-Safe mode. If
WDTO is [0], the device is in Normal mode (assuming
device is powered and not in the Sleep mode), with the
watchdog either enabled or disabled.
Previous Address SOA[2:0]=110
SOA3 = 0. OD2 to OD0 return the state of the IN, FSI, and
WAKE terminals, respectively (
Table 10
).
SOA3 = 1. The returned data contains the programmed
values in the UOVR register. Bit OD1 reflects the state of
the undervoltage protection, while bit OD0 reflects the
state of the overvoltage protection (refer to
Table 8
,
page 19).
Previous Address SOA[2:0]=111
Null Data. No previous register Read Back command
received, so bits OD2, OD1, and OD0 are null, or 000.
MODES OF OPERATION
The 33982 has four operating modes. They are Sleep,
Normal, Fault, and Fail-Safe.
Table 11
summarizes details
contained in succeeding paragraphs.
Sleep Mode
The default mode of the 33982 is the Sleep mode. This is the
state of the device after first applying battery voltage (V
PWR
),
prior to any I/O transitions. This is also the state of the device
when the WAKE and
RST
are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are off to minimize current draw. In addition, all
SPI-configurable features of the device are as if set to logic [0].
The device will transition to the Normal or Fail-Safe operating
modes based on the WAKE and
RST
inputs as defined in
Table 11
.
Normal Mode
The 33982 is in Normal mode when:
V
PWR
is within the normal voltage range.
RST
terminal is logic [1].
No fault has occurred.
Fail-Safe Mode
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or
RST
input terminal
transitions from logic [0] to [1]. The WAKE input is capable of
being pulled up to V
PWR
with a series of limiting resistance that
limits the internal clamp current.
The watchdog timeout is a multiple of an internal oscillator
and is specified in
Table 7
,
page 18
.
As long as the WD bit (D7)
of an incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the programmed
value of the WDR the device will operate normally. If an internal
watchdog timeout occurs before the WD bit, the device will
revert to a Fail-Safe mode until the device is reinitialized.
Table 10. Terminal Register
OD2
OD1
OD0
IN Terminal
FSI Terminal
WAKE Terminal
Table 11. Fail-Safe Operation and Transitions
to Other 33982 Modes
Mode
FS
WAKE
RST
WDTO
Comments
Sleep
x
0
0
x
Device is in Sleep mode.
All outputs are OFF.
Normal
1
x
1
No
Normal mode. Watchdog
is active if enabled.
Fault
0
1
x
No
The device is currently in
fault mode. The faulted
output is OFF.
0
x
1
Fail-
Safe
1
0
1
Yes
Watchdog has timed out
and the device is in Fail-
Safe mode. The output is
as configured with the
RFS resistor connected to
FSI.
RST
and WAKE must
be transitioned to logic [0]
simultaneously to bring
the device out of the Fail-
Safe mode or momentarily
tied the FSI terminal to
ground.
1
1
1
1
0
1
1
1
0
x = Don’t care.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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