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參數(shù)資料
| 型號(hào)： | MC34982PNA |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 mOhm)(單智能大電流帶自保護(hù)功能的硅高端開關(guān)（2mOhm）) |
| 中文描述： | 單智能大電流的自我保護(hù)硅高邊開關(guān)（2.0毫歐）（單智能大電流帶自保護(hù)功能的硅高端開關(guān)（2mOhm）） |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 771K |
| 代理商： | MC34982PNA |
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the corresponding message bits when addressing the OCR
register.
The DICR register is useful if there is a need to
independently turn on and off several loads that are PWM’d at
the same frequency and duty cycle with only one PWM signal.
This type of operation can be accomplished by connecting the
pertinent direct IN terminals of several devices to a PWM output
port from the MCU and configuring each of the outputs to be
controlled via their respective direct IN terminal. The DICR is
then used to Boolean AND the direct IN(s) of each of the
outputs with the dedicated SPI bit that also controls the output.
Each configured SPI bit can now be used to enable and disable
the common PWM signal from controlling its assigned output.
A logic [1] on bit D2 is used to select the high ratio (C
SR1
,
1/40000) on the CSNS terminal. The default value [0] is used to
select the low ratio (C
SR0
, 1/5400). A logic [1] on bit D3 is used
to select the high-speed slew rate. The default value [0]
corresponds to the low speed slew rate.
Address 0101—Output Switching Delay Register (OSDR)
The OSDR register is used to configure the device with a
programmable time delay that is active during Output On
transitions that are initiated via SPI (not via direct input).
Whenever the input is commanded to transition from [0] to [1],
the output will be held OFF for the time delay configured in the
OSDR register.
The programming of the contents of this register has no
effect on device Fail-Safe mode operation. The default value of
the OSDR register is 000, equating to no delay, since the
switching delay time is 0 ms. This feature allows the user a way
to minimize inrush currents, or surges, thereby allowing loads to
be synchronously switched ON with a single command.
Table 6
shows the eight selectable output switching delay
times, which range from 0 ms to 525 ms.
Address 1101—Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
watchdog timeout. Watchdog timeout is configured using bits
D1 and D0 (
Table 7
). When bits D1and D0 are programmed for
the desired watchdog timeout period, the WD bit (D7) should be
toggled as well to ensure that the new timeout period is
programmed at the beginning of a new count sequence.
Address 0110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy chain SPI configuration. This allows devices
to not be affected by commands being clocked over a daisy-
chained SPI configuration, and by toggling the WD bit (D7) the
watchdog circuitry will continue to be reset while no
programming or data readback functions are being requested
from the device.
Address 1110—Undervoltage/Overvoltage Register
(UOVR)
The UOVR register can be used to disable or enable the
overvoltage and/or undervoltage protection. By default ([0]),
both protections are active. When disabled, an undervoltage or
overvoltage condition fault will not be reported in bits D1 and D0
of the output fault register.
Address x111—TEST
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
Serial Output Communication (Device Status Return
Data)
When the
CS
terminal is pulled low, the output status register
is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI terminal. The
first eight bits of data clocking out of the SO, and following a
CS
transition, are dependant upon the previously written SPI word.
Any bits clocked out of the SO terminal after the first eight will
be representative of the initial message bits clocked into the SI
terminal since the
CS
terminal first transitioned to a logic [0].
This feature is useful for daisy chaining devices as well as
message verification.
A valid message length is determined following a
CS
transition of [0] to [1]. If there is a valid message length, the data
is latched into the appropriate registers. A valid message length
is a multiple of eight bits. At this time, the SO terminal is tri-
stated and the fault status register is now able to accept new
fault status information.
The output status register correctly reflects the status of the
STATR-selected register data at the time the
CS
is pulled to a
Table 6. Switching Delay
OSD[2:0] (D2, D1, D0)
Timing (ms)
000
0
001
75
010
150
011
225
100
300
101
375
110
450
111
525
Table 7. Watchdog Timeout
WD[1:0] (D1, D0)
Timing (ms)
00
620
01
310
10
2500
11
1250
F
Freescale Semiconductor, Inc.
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