參數(shù)資料
型號: MC33989
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip with High Speed CAN Transceiver(帶高速CAN收發(fā)器的系統(tǒng)基片)
中文描述: 系統(tǒng)基礎(chǔ)芯片的高速CAN收發(fā)器(帶高速的CAN收發(fā)器的系統(tǒng)基片)
文件頁數(shù): 22/32頁
文件大?。?/td> 676K
代理商: MC33989
22
MC33989
MC33989
7.1.1
MCR register
Control bits:
(1): Bit BATFAIL cannot be set by SPI. BATFAIL is set when Vsup falls below 3V.
(2): Watchdog ON or OFF depends upon RCR register bit D3.
(3): Before entering sleep mode, bit BATFAIL in MCR register must be previously cleared (MCR read operation), and bit
NOSTOP in RCR register must be previously set to 1.
Status bits:
7.1.2
RCR register
MCR
D3
D2
D1
D0
$000b
W
MCTR2
MCTR1
MCTR0
R
BATFAIL
(1)
VDDTEMP
GFAIL
WDRST
Reset value
0
0
0
Reset condition
POR, RESET
POR, RESET
POR, RESET
MCTR2
MCTR1
MCTR0
SBC mode
Description
0
0
0
Enter/leave debug mode
To enter or leave debug mode, refer to detail
description in chapter 4.
0
0
1
Normal
0
1
0
Standby
0
1
1
Stop, watchdog off
(2)
0
1
1
Stop, watchdog on
(2)
1
0
0
Sleep
(3)
1
0
1
Normal
No watchdog running, debug mode
1
1
0
Standby
1
1
1
Stop
Status bit
Description
GFAIL
Logic OR of CAN failure (TXF permanent dominant or CAN over
current or CAN therm) or HS1 over temp or V2 low
BATFAIL
Battery fail flag (set when Vsup < 3V)
VDDTEMP
Temperature pre-warning on VDD (latched)
WDRST
Watchdog reset occurred
RCR
D3
D2
D1
D0
$001b
W
WDSTOP
NOSTOP
SAFE
RSTTH
R
Reset value
1
0
0
0
Reset condition
POR, RESET,
STO2NR
POR, NR2N,
NR2STB
POR
POR
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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