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參數(shù)資料
| 型號(hào)： | MC33989 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip with High Speed CAN Transceiver(帶高速CAN收發(fā)器的系統(tǒng)基片) |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的高速CAN收發(fā)器（帶高速的CAN收發(fā)器的系統(tǒng)基片） |
| 文件頁(yè)數(shù)： | 21/32頁(yè) |
| 文件大?。?/td> | 676K |
| 代理商： | MC33989 |
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MC33989
21
MC33989
7
7.1
SPI INTERFACE AND REGISTER DESCRIPTION
Data format description
The SPI is a 8 bit SPI. First 3 bits are used to identify the internal SBC register adress, bit 4 is a read/write bit. The last 4 bits
are data send from MCU to SBC or read back from SBC to MCU.
During write operation state of MISO has no signification.
During read operation only the last 4 bits at MISO have a meaning (content of the accessed register)
Following tables describe the SPI register list, and register bit meaning.
Registers “reset value” is also described, as well as the “reset condition”. Reset condition is the condition which cause the bit
to be set at the “reset value”.
Possible reset condition are:
SBC
reset:
Power On Reset: POR
SBC
mode transition:
NR2R - Normal Request to Reset mode
NR2N - Normal Request to Normal mode
NR2STB - Normal Request to Standby mode
N2R - Normal to Reset mode
STB2R - Standby to Reset mode
STO2R - Stop to Reset mode
STO2NR - Stop to NormalRequest
SBC mode:
RESET - SBC in Reset mode
List of Registers:
Name
Adress
Description
Comment and usage
MCR
$ 0 0 0
Mode control register
Write: Control of normal, standby, sleep, stop, debug modes
Read: BATFAIL flag and other status bits and flags
RCR
$ 0 0 1
Reset control register
Write: Configuration for reset voltage level, safe bit, stop mode
Read: CAN wake up and CAN failure status bits
CAN
$ 0 1 0
CAN control register
Write: CAN module control: Tx/Rx & sleep modes, slope control, wake
enable/disable.
Read: CAN wake up and CAN failure status bits
IOR
$ 0 1 1
I/O control register
Write: HS1 (high side switch) control in normal and standby mode
Read: HS1 over temp bit, Vsup and V2 low status.
WUR
$ 1 0 0
Wake up input regis-
ter
Write: Control of wake up input polarity
Read: Wake up input, and real time Lx input state
TIM
$ 1 0 1
Timing register
Write: TIM1, Watchdog timing control, window or Timeout mode.
Write: TIM2, Cyclic sense and force wake up timing selection
LPC
$ 1 1 0
Low power mode
control register
Write: Control of HS1 periodic activation in sleep and stop modes, force
wake up.
INTR
$ 1 1 1
Interrupt register
Write: Interrupt source configuration
Read: INT source
Table 7-1.
MOSI
MISO
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
D0
D1
D2
D3
R/W
A0
A1
A2
data
address
Read operation: R/W bit = 0
Write operation: R/W bit = 1
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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