參數(shù)資料
型號(hào): MC33389
廠(chǎng)商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: System Basis Chip with Low Speed Fault Tolerant CAN(帶低速容錯(cuò)CAN接口的系統(tǒng)基片)
中文描述: 系統(tǒng)基礎(chǔ)芯片與低速容錯(cuò)CAN(帶低速容錯(cuò)的CAN接口的系統(tǒng)基片)
文件頁(yè)數(shù): 23/35頁(yè)
文件大小: 591K
代理商: MC33389
MC33389
MOTOROLA
23
MC33389
Freescale Semiconductor, Inc.
Table 28. MCR —Mode Control Register
MCR and MCVR registers are used to control the mode of the SBC. To change the operating mode of the SBC, both
registers must have the same content. The order of writing the registers has to be taken into account. To set the SBC mode
properly, MCR has to be written first then followed by MCVR write. A write operation sets the MCR and MCVR registers, a read
operation perform a read out of the current status (MSR - mode status register).
The Emergency mode is a regular mode.
A reset of both MCR and MCVR registers occurs when RSTB = low and the SBC is set to NormalRequest mode.
Table 29. MCVR — Mode Control Validating Register
Table 30.
Table 31. V3R — V3R Control Register
This register is used to configure the state of V3 high side switch in normal and standby modes, and the V3 operation and the
Forced wake up or the cyclic sense option for the sleep mode operation.
Table 32.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MCR
$000
R
MSR2
MSR1
MSR0
W
MCR2
MCR1
MCR0
RESET
0
0
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MCVR
$003
R
MSVR2
MSVR1
MSVR0
W
MCR2
MCR1
MCR0
RESET
0
0
0
MC(V)R2
MC(V)R1
MC(V)R0
MSR2
MSR1
MSR0
Automatically entered after reset
NormalRequest
0
0
0
0
0
1
Normal
0
0
1
0
1
0
Standby
0
1
0
1
0
0
Sleep
1
0
0
1
1
1
Emergency
1
1
1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V3R
$005
R
WI2V3
FWU
CYS
V3R0
W
RESET
1
0
0
0
WI2V3
FWU
CYS
V3R0
Comments
X
0
0
0
V3 off
Only In Normal And Standby
Mode Available
X
0
0
1
V3 on
X
X
1
X
Cyclic Sense On
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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