參數(shù)資料
型號(hào): MC33389
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: System Basis Chip with Low Speed Fault Tolerant CAN(帶低速容錯(cuò)CAN接口的系統(tǒng)基片)
中文描述: 系統(tǒng)基礎(chǔ)芯片與低速容錯(cuò)CAN(帶低速容錯(cuò)的CAN接口的系統(tǒng)基片)
文件頁(yè)數(shù): 22/35頁(yè)
文件大?。?/td> 591K
代理商: MC33389
MC33389
22
MC33389
Freescale Semiconductor, Inc.
the MOSI pin starting with Bit15, followed by Bit14, Bit13, etc.,
to Bit0. For each fall of the SCLK signal, with CSB held in a
logic low state, a databit is loaded into the shift register per the
databit MOSI state.The shift register is full after sixteen bits of
information have been entered.
MISO Pin
The serial output (MISO) pin is the tri-stateable output
from the shift register. The MISO pin remains in a high
impedance state until the CSB pin goes to a logic low state.
The MISO pin changes state on the rising edge of SCLK and
reads out on the falling edge of SCLK. The MOSI/MISO
shifting of data follows a first-in-first-out protocol with both
input and output words transferring the MSB first.
Module Address Map, the module address map is shown
in table below.
Table 27. Module Address Map
Address
Register
Register
Name
$000
Mode Control Register
MCR
$003
Mode Control Validation
RegisterMCVR
MCVR
$005
V3 control register
V3R
$006
Cyclic timing control register
CYTCR
$009
Software watchdog
control register
SWCR
$00A
Ground shift level register
GSLR
$00C
Wake-up input control register
WUICR
$00F
Wake-up input status register
WUISR
$011
Wake up input real time information
WUIRTI
$012
Overtemperature status register
OTSR
$014
Transceiver error status
register for CANH
TESRH
$017
Transceiver error status
register for CANL
TESRL
$018
Reset source register
RSR
$01B
Voltage supply status register
VSSR
$01D
Interrupt mask control register 1
IMR1
$01E
Interrupt mask control register 2
IMR2
$021
Interrupt source register 1
ISR1
$022
Interrupt source register 2
ISR2
$024
Transceiver control register
TCR
F
For More Information On This Product,
Go to: www.freescale.com
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