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參數(shù)資料
| 型號(hào)： | MC33298P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | OCTAL SERIAL SWITCH (SPI Input/Output) |
| 中文描述： | 1 A 8 CHANNEL, SIPO BASED PRPHL DRVR, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | MC33298P |
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MC33298
7
MOTOROLA ANALOG IC DEVICE DATA
(Low–to–High)
SO
CL = 200 pF
VDD = 5.0 V
SCLK
MC33298
Under
Test
CL represents the total capacitance of the test fixture and probe.
tfSI
trSI
0.2 VDD
0.7 VDD
0.2 VDD
0.7 VDD
tfSO
tvalid
trSO
VOL
VOH
VOL
VOH
tdly(hl)
tdly(lh)
0.2 VDD
0.7 VDD (2.5 V)
0
5.0 V
≤
10 ns
50%
≤
10 ns
SO (low–to–high) is for an output with internal conditions such that
the low–to–high transition of CSB causes the SO output to switch
from high–to–low.
SO
CL = 20 pF
RL = 2.0 k
VPull–Up = 2.5 V
VDD = 5.0 V
CSB
MC33298
Under
Test
CL represents the total capacitance of the test fixture and probe.
trSI
tfSI
VOL
VOH
VOL
VOH
0
5.0 V
SO
(Low–to–High)
tSO(dis)
tSO(en)
tSO(dis)
tSO(en)
(High–to–Low)
0.7 VDD
0.2 VDD (2.5 V)
≤
10 ns
≤
10 ns
CSB
NOTES
: 1. SO (high–to–low) waveform is for SO output with internal
conditions such that SO output is low except when an output is
disabled as a result of detecting a circuit fault with CSB in a
High Logic state (e.g., open load).
2.SO (low–to–high) waveform is for SO output with internal
conditions such that SO output is high except when an output
is disabled as a result of detecting a circuit fault with CSB in
a High Logic state (e.g., shorted load).
50%
50%
90%
50%
10%
SO
SO
SCLK
(High–to–Low)
SO
Figure 3. Valid Data Delay Time and
Valid Time Test Circuit
Figure 4. Enable and Disable Time Test Circuit
Figure 5. Vaild Data Delay Time and
Valid Time Waveforms
Figure 6. Enable and Disable Time Waveforms
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