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參數(shù)資料
| 型號： | MC2800 |
| 廠商： | Motorola, Inc. |
| 英文描述： | FSK FM IF Receiver(FSK FM IF 接收器) |
| 中文描述： | FSK信號調(diào)頻（FSK信號調(diào)頻中頻接收器中頻接收機(jī)） |
| 文件頁數(shù)： | 22/28頁 |
| 文件大小： | 473K |
| 代理商： | MC2800 |
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MC2800
22
MOTOROLA RF/IF DEVICE DATA
BRF Out
Input
–2.5 ms
0 s
2.5 ms
1
2
BRF Out
D1
D2
4.8 k
D1 =
D2 = 0
1.6 k
D1 = 0
D2 = 1
–4.8 k
D1 = 1
D2 = 0
–1.6 k
D1 = 1
D2 = 1
–2.5 ms
0 s
2.5 ms
1
2
3
Figure 16. Modulation and Signal
at BRF Out Pin
Figure 17. Digital D1 and D2 Outputs
EN and CL Timing Requirements
When power is first applied to the MC2800 the capacitor
connecting to the Pin PH Cont is pre–charged to 0.9 V. The
voltages at Pins EN and CL must be set to high during this
Power On cycle of time. In the typical system application as
shown in Figure 6 the voltage at Pin EN is pulled to high for a
duration of 60 seconds at first. During this period the device
MC2800 is enabled and data at Pins D1 and D2 is valid 6.0 ms
after EN is high. When EN goes high, CL can also go high at
the same instance without any delay. The purpose of pulling
CL to high is to set up the voltages at Pins 31 and 32. It has
been tried that 4.0 ms is adequate to get these pins to the
correct voltages. However some delay must be allowed for
the transient to die down after CL goes low. In application, it
is observed that the data D1 and D2 will be valid 2.0 ms after
CL goes low in this receive cycle. When there is no incoming
message to receive, it is best to disable the MC2800 to save
power. In this idle cycle, the MC2800 is disabled most of the
time and it is enabled once every 1.5 s (or in some cases
1.875 s) to open the channel for the MCU to detect if there is
any message coming in or not. These typical conditions are
all illustrated in Figure 18.
EN
CL
Data D1 and D2 is valid 2.0 ms
after CL goes low.
2.0 ms
4.0 ms
D1, D2
PH Cont
Power–On Cycle
Receive Cycle
Idle Cycle
60 s
1.4 s
0.1 s
Figure 18. Timing of EN and CL
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