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參數(shù)資料
| 型號： | MC145745FW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 調制器/解調器 |
| 英文描述： | V.21/V.23 Telemeter Modem |
| 中文描述： | 1.2 kbps DATA, MODEM, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 172K |
| 代理商： | MC145745FW |
MC145745
10
MOTOROLA
Figure 5. Serial Control Port Read Operation
SCPCLK
SCPEN
SCP Tx
A2
A1
A0
R/W
HIGH IMPEDANCE
D3
D2
D1
D0
SCP Rx
Figure 6. Serial Control Port Write Operation
SCPCLK
SCPEN
A2
A1
A0
R/W
HIGH IMPEDANCE
D3
D2
D1
D0
SCP Rx
SCP Tx
DESCRIPTION OF THE SCP TERMINAL
The SCP bus is made up of the following four pins.
SCP Tx (Pin 20)
The SCP Tx pin outputs the control, status, and data in-
formation from the 4–bit wide register. During the read action
transaction, a R/W bit and the three address bits are shifted
in from SCP Rx at four SCPCLK rising edges, subsequent to
SCPEN going low. After this, if a read operation is selected,
SCP Tx comes out of the high impedance state at the first
falling edge of SCPCLK, and outputs the first bit (MSB) of the
chosen register. The remaining three bits of the chosen reg-
ister are shifted out from SCP Tx at the following three
SCPCLK falling edges. After the last bit (LSB) is shifted out,
SCPEN must return to high. Then SCP Tx returns to the high
impedance condition.
SCP Rx (Pin 21)
The SCP Rx pin is used to input control and data informa-
tion into the 4–bit wide register. Data is shifted in from
SCP Rx at SCPCLK rising edge, while SCPEN is low. The
first bit is the R/W bit (1 = read, 0 = write), and the next three
bits address one of seven byte–registers. The address bits
are shifted in MSB first. If the write action is chosen, the 4–bit
data is shifted in from SCP Rx at the next four SCPCLK rising
edges. If the read action is chosen, 4–bit data in the selected
register is shifted out on SCP Tx. SCP Rx is ignored while
SCPEN is high.
SCPCLK (Pin 22)
The SCPCLK pin is an input of standard clock for hand-
shaking between SCP and MCU. After SCPEN comes low
and the SCP transaction occurs, data is shifted from SCP Rx
into the device at the rising edge of SCPCLK, and is shifted
out on SCP Tx at the falling edge of SCPCLK. When SCPEN
is high, SCPCLK is ignored (i.e., it may be continuous or it
can operate in the burst mode).
SCPEN (Pin 23)
When the SCPEN pin is held low, the SCP transaction is
enabled and control, status, and data information is trans-
ferred. If SCPEN is returned to high, the SCP action in prog-
ress is aborted, and the SCP Tx pin enters a high impedance
condition.
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