參數(shù)資料
型號(hào)： MC145193
廠商： Motorola, Inc.
英文描述： 1.1GHz PLL Frequency Synthesizer(1.1GHz PLL頻率合成器)
中文描述： 1.1GHz的鎖相環(huán)頻率合成器（1.1GHz的鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 13/23頁(yè)
文件大?。?/td> 269K
代理商： MC145193
MC145193
13
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS – RF AND IF DEVICE DATA
ENB
CLK
Din
MSB
LSB
C7
C6
C5
C4
C3
C2
C1
C0
1
2
3
4
5
6
7
8
NOTE
NOTE:
At this point, the new byte is transferred to the C register and stored. No other
registers are affected.
Figure 14. C Register Access and Format
(8 Clock Cycles are Used)
C7 – POL:
Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PDout
and interchanges the
φ
R function with
φ
V as depicted in Figure 17. Also see the phase detector output
pin descriptions for more information. This bit is cleared low at power up.
C6 – PDA/B:
Selects which phase/frequency detector is to be used. When set high, enables the output of
phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing
φ
R and
φ
V
to the static high state. When cleared low, phase/frequency detector B is enabled (
φ
R and
φ
V) and
phase/frequency detector A is disabled with PDout forced to the high–impedance state. This bit is
cleared low at power up.
C5 – LDE:
Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced
to a static low level. This bit is cleared low at power up.
C4 – STBY:
When set, places the CMOS section of device, which is powered by the VDD and VPD pins, in the
standby mode for reduced power consumption: PDout is forced to the high–impedance state,
φ
R and
φ
V are forced high, the A, N, and R counters are inhibited from counting, and the Rx current is shut
off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change). C5 high
forces LD static high. During standby, data is retained in the A, R, and C registers. The condition
of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and R15. However,
if REFout = static low is selected, the internal feedback resistor is disconnected and the input is inhibited
when in standby; in addition, the REFin input only presents a capacitive load. NOTE: Standby does
not affect the other modes of the REF/OSC circuitry.
When C4 is reset low, the part is taken out of standby in two steps. First, the REFin (only in one
mode) resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any fR and
fV signals are inhibited from toggling the phase/frequency detectors and lock detector. Second, when
the first fV pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors
are initialized. Immediately after the jam load, the A, N, and R counters begin counting down together.
At this point, the fR and fV pulses are enabled to the phase and lock detectors. (Patented feature.)
C3, C2 – I2, I1:
Controls the PDout source/sink current per Tables 5 and 6. With both bits high, the maximum current
is available. Also, see C1 bit description.
C1 – Port:
When the Output A pin is selected as “Port” via bits A22 and A23, C1 determines the state of Output
A. When C1 is set high, Output A is forced high; C1 low forces Output A low. When Output A is
not
selected as “Port,” C1 controls whether the PDout step size is 10% or 25%. (See Tables 5 and
6.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when Output A is
selected as “Port.” The Port bit is not affected by the standby mode.
C0 – Out B:
Determines the state of Output B. When C0 is set high, Output B is high–impedance; C0 low forces
Output B low. The Out B bit is not affected by the standby mode. This bit is cleared low at power
up.
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