參數(shù)資料
型號(hào)： MC145190
廠商： Motorola, Inc.
英文描述： 1.1 GHz PLL Frequency Synthesizers
中文描述： 1.1 GHz PLL頻率合成器
文件頁(yè)數(shù)： 16/24頁(yè)
文件大?。?/td> 341K
代理商： MC145190
MC145190
MC145191
16
MOTOROLA
ENB
CLK
Din
1
2
3
4
5
6
7
8
MSB
LSB
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
R11
R12
R13
R14
R15
9
10
11
12
13
14
15
16
0
0
0
0
0
0
0
0
0
·
·
·
F
F
0
0
0
0
0
0
0
0
0
·
·
·
F
F
0
1
2
3
4
5
6
7
8
·
·
·
E
F
NOT ALLOWED
R COUNTER =
÷
1 (NOTE 6)
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
R COUNTER =
÷
5
R COUNTER =
÷
6
R COUNTER =
÷
7
R COUNTER =
÷
8
R COUNTER =
÷
8190
R COUNTER =
÷
8191
HEXADECIMAL VALUE
0
0
0
0
0
0
0
0
0
·
·
·
1
1
BINARY VALUE
0
1
2
3
4
5
6
7
CRYSTAL MODE, SHUT DOWN
CRYSTAL MODE, ACTIVE
REFERENCE MODE, REFin ENABLED and REFout
STATIC LOW
REFERENCE MODE, REFout = REFin (BUFFERED)
REFERENCE MODE, REFout = REFin/2
REFERENCE MODE, REFout = REFin/4
REFERENCE MODE, REFout = REFin/8 (NOTE 3)
REFERENCE MODE, REFout = REFin/16
OCTAL VALUE
NOTES:
1. Bits R15 through R13 control the configurable “OSC or 4–stage divider” block (see Block Diagram).
2. Bits R12 through R0 control the “13–stage R counter” block (see Block Diagram).
3. A power–on initialize circuit forces a default REFin to REFout ratio of eight.
4. At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 through
R12 are loaded into the first buffer in the double–buffered section of the R register. Therefore, the R counter divide ratio is not altered
yet and retains the previous ratio loaded. The C and A registers are not affected.
5. At this point, bits R0 through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio
after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. Also, see note 3 of Figure 16 for
an alternate method of loading the second buffer in the R register. The C and A registers are not affected. The first buffer of the R register
is not affected.
6. Allows direct access to reference input of phase/frequency detectors.
NOTE
4
NOTE
5
Figure 17. R Register Access and Format (16 Clock Cycles Are Used)
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