參數(shù)資料
型號: MC145190
廠商: Motorola, Inc.
英文描述: 1.1 GHz PLL Frequency Synthesizers
中文描述: 1.1 GHz PLL頻率合成器
文件頁數(shù): 12/24頁
文件大?。?/td> 341K
代理商: MC145190
MC145190
MC145191
12
MOTOROLA
100 ns MINIMUM
1
2
4
5
3
1
2
4
5
3
1
2
4
5
3
Figure 13. Initializing the PLL through the Serial Port
NOTE: It may not be convenient to control the ENB or CLK pins during power up per the Pin Descriptions. If this is the case, the part may
be initialized through the serial port as shown in the figure above. The sequence is similar to accessing the registers except that the
CLK must remain high at least 100 ns after ENB is brought high. Note that 3 groups of 5 bits are needed.
CLK
Din
ENB
MC145190
Nominal PDout Spurious Current vs fR Frequency
(1 V
PDout
fR
(kHz)
VPD – 1 V)
Current
(RMS nA)
10
1.6
20
5.3
50
22
100
95
200
320
MC145191
Nominal PDout Spurious Current vs fR Frequency
(1 V
PDout
fR
(kHz)
VPD – 1 V)
Current
(RMS nA)
10
3.6
20
4.6
50
17
100
75
200
244
NOTE: For information on spurious current measurement see AN1253/D, “An Improved PLL Design Method Without
ω
n and
ζ
”.
Table 2. PDout Current, C1 = Low with OUTPUT A NOT
Selected as “Port”; Also, Default Mode When
OUTPUT A Selected as “Port”
C3
C2
PDout Current
70%
0
0
0
1
80%
1
0
90%
1
1
100%
Table 3. PDout Current, C1 = High with OUTPUT A NOT
Selected as “Port”
C3
C2
PDout Current
0
0
25%
0
1
50%
1
0
75%
1
1
100%
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