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參數(shù)資料
| 型號(hào)： | MC145162D1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 85 MHz, PDSO16 |
| 封裝： | SOG-16 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 223K |
| 代理商： | MC145162D1 |
MC145162
MC145162–1
14
MOTOROLA
Tx/Rx CHANNEL COUNTER TEST
In normal applications, the TxPS/fTx and the RxPS/fRx out-
put pins indicate the power saving mode status. However, the
user can examine the Tx and Rx channel counter outputs by
setting the Test bit in the control register to 1. The final value
of the transmit–channel counter and the receive–channel
counter multiplex out to TxPS/fTx and RxPS/fRx respectively.
The user can verify the divided–down output waveform asso-
ciated with the RF input level in the PLL circuitry implementa-
tion (Figure 18).
fin–R
16–BIT Rx PROGRAMMABLE
CHANNELS COUNTER
RxPS
RxPS/fRx
fRx
16–BIT Tx PROGRAMMABLE
CHANNELS COUNTER
fin–T
TxPS
TxPS/fTx
fTx
IF TEST BIT IS SET TO 1, THE fTx
AND fRx ARE MUXED OUT AT PINS
TxPS/fTx AND RxPS/fRx,
RESPECTIVELY, FOR Rx/Tx
CHANNEL COUNTER TEST.
CONTROL REGISTER IDENTIFIER = 1
REF PD
ENABLE
RxPD
ENABLE
TxPD
ENABLE
1
0
TEST
BIT
AUX
DATA
SELECT
CONTROL REGISTER
Din
REF
OUT
3/
Figure 18. RF Buffer Sensitivity
4
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