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參數(shù)資料
| 型號： | MC145162D1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 85 MHz, PDSO16 |
| 封裝： | SOG-16 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 223K |
| 代理商： | MC145162D1 |
MC145162
MC145162–1
10
MOTOROLA
Figure 12. Programming Format for Control Register (3–Pin Interfacing Scheme)
AUX DATA SELECT = 0
ENB
CONTROL REGISTER IDENTIFIER = 1
REF PD
ENABLE
RxPD
ENABLE
TxPD
ENABLE
1
0
TEST
BIT
AUX
DATA
SELECT
CONTROL REGISTER DATA
Din
REF
OUT
3/
MSB
LSB
CLK
NOTE: ENB must be high during the serial transfer.
4
16–BIT Rx COUNTER
DIVIDE RATIO
Din
ENB
16–BIT Tx COUNTER
DIVIDE RATIO
Figure 13. Programming Format for Transmit and Receive Counters
(3–Pin Interfacing Scheme)
CLK
NOTE: ENB must be low during the serial transfer.
LAST
CLOCK
CONTROL REGISTER IDENTIFIER = 1
REF PD
ENABLE
RxPD
ENABLE
TxPD
ENABLE
AUX
DATA
SELECT
REF
OUT
3/
1
Din
ENB
CONTROL REGISTER DATA
AUX DATA SELECT = 1
MSB
LSB
Figure 14. Programming Format for Control Register (4–Pin Interfacing Scheme)
CLK
NOTE: ENB must be high during the serial transfer.
0
TEST
BIT
4
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| MC145166DW | 制造商:Motorola Inc 功能描述:PLL FREQUENCY SYNTHESIZER, 60 MHz, PDSO16 |
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