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參數(shù)資料
| 型號： | MC145156-2 |
| 廠商： | Motorola, Inc. |
| 英文描述： | PLL Frequency Synthesizer(PLL頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器（PLL頻率合成器） |
| 文件頁數(shù)： | 3/26頁 |
| 文件大小： | 423K |
| 代理商： | MC145156-2 |
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MC145151–2 through MC145158–2
MOTOROLA
3
14 x 8 ROMREFERENCE DECODER
14–BIT
÷
N COUNTER
φ
V
φ
R
MC145151–2 BLOCK DIAGRAM
14–BIT
÷
R COUNTER
TRANSMIT OFFSET ADDER
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PDout
RA2
RA1
fin
VDD
OSCin
OSCout
T/R
14
14
fV
N13
N11
N9
N7 N6
N4
N2
N0
NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.
RA0
PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 1)
Input to the
÷
N portion of the synthesizer. fin is typically
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RA0 – RA2
Reference Address Inputs (Pins 5, 6, 7)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below.
Pull–up resistors ensure that inputs left open remain at a
logic 1 and require only a SPST switch to alter data to the
zero state.
Reference Address Code
Total
Divide
Value
RA2
RA1
RA0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
128
256
512
1024
2048
2410
8192
N0 – N11
N Counter Programming Inputs (Pins 11 – 20, 22 – 25)
These inputs provide the data that is preset into the
÷
N
counter when it reaches the count of zero. N0 is the least sig-
nificant and N13 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only
an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at
the N inputs. This is normally used for offsetting the VCO
frequency by an amount equal to the IF frequency of the
transceiver. This offset is fixed at 856 when T/R is low and
gives no offset when T/R is high. A pull–up resistor ensures
that no connection will appear as a logic 1 causing no offset
addition.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSCout to ground.
OSCin may also serve as the input for an externally–gener-
ated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSCout.
OUTPUT PINS
PDout
Phase Detector A Output (Pin 4)
Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this pur-
pose (see
φ
V and
φ
R).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
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PDF描述 |
|---|---|
| MC145157-2 | PLL Frequency Synthesizer(PLL頻率合成器) |
| MC145158-2 | PLL Frequency Synthesizer(PLL頻率合成器) |
| MC145158DW | Serial-Input PLL Frequency Synthesizer |
| MC145158P2 | Parallel-Input PLL Frequency Synthesizer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145158-2 | 制造商:Motorola Inc 功能描述: |
| MC145158DW2 | 功能描述:IC SER-IN PLL FREQ SYNTH 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145158DW2R2 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC145159FN1R2 | 制造商:Motorola Inc 功能描述: |
| MC145159P1 | 制造商:Motorola Inc 功能描述: |
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