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參數(shù)資料
| 型號(hào)： | MC145155DW2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Parallel-Input PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 22 MHz, PDSO20 |
| 封裝： | SOG-20 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC145155DW2 |
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MC145151–2 through MC145158–2
28
MOTOROLA
DESIGN CONSIDERATIONS
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
C)
_
+A
C
R2
C
VCO
C
VCO
R2
B)
A)
C
VCO
PDout
PDout
φ
R —
φ
V —
PDout —
φ
R
φ
V
R1
R1
R1
R1
R2
NOTE: Sometimes R1 is split into two series resistors, each R1
÷
2. A capacitor CC is then placed from the midpoint to ground to further
filter
φ
V and
φ
R. The value of CC should be such that the corner frequency of this network does not significantly affect
ω
n.
The
φ
R and
φ
V outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
DEFINITIONS:
N = Total Division Ratio in feedback loop
K
φ
(Phase Detector Gain) = VDD/
4
π
for PDout
K
φ
(Phase Detector Gain) = VDD/2
π
for
φ
V and
φ
R
2
π
fVCO
VVCO
for a typical design wn (Natural Frequency)
≈
2
π
fr
Damping Factor:
ζ
1
KVCO (VCO Gain) =
10
(at phase detector input).
RECOMMENDED READING:
Gardner, Floyd M.,
Phaselock Techniques (second edition).
New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim,
Frequency Synthesizers: Theory and Design (second edition).
New York, Wiley–Interscience, 1980.
Blanchard, Alain,
Phase–Locked Loops: Application to Coherent Receiver Design.
New York, Wiley–Interscience, 1976.
Egan, William F.,
Frequency Synthesis by Phase Lock.
New York, Wiley–Interscience, 1981.
Rohde, Ulrich L.,
Digital PLL Frequency Synthesizers Theory and Design.
Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M.,
Design of Phase–Locked Loop Circuits, with Experiments.
Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold,
The PLL Synthesizer Cookbook.
Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from
Electronic Design,
1987.
φ
R —
φ
V —
F(s) =
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =
ζ
=
ω
n =
NR1C
R1sC + 1
ω
n =
ζ
=
ω
nR2C
2
R2sC + 1
R1sC
1
N
ω
n
2K
φ
KVCO
F(s) =
ζ
=
ω
n =
(R1+ R2)sC + 1
R2sC + 1
NC(R1 + R2)
R2C +
N
K
φ
KVCO
K
φ
KVCO
NCR1
0.5
ω
n
K
φ
KVCO
K
φ
KVCO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145156P2 | Parallel-Input PLL Frequency Synthesizer |
| MC145151FN2 | Parallel-Input PLL Frequency Synthesizer |
| MC145152DW2 | Parallel-Input PLL Frequency Synthesizer |
| MC145155P2 | CONNECTOR ACCESSORY |
| MC145157P2 | Parallel-Input PLL Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145155P | 制造商:Motorola Inc 功能描述: |
| MC145158-2 | 制造商:Motorola Inc 功能描述: |
| MC145158DW2 | 功能描述:IC SER-IN PLL FREQ SYNTH 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145158DW2R2 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC145159FN1R2 | 制造商:Motorola Inc 功能描述: |
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